FORMING FINS OF DIFFERENT MATERIALS ON THE SAME SUBSTRATE

• US 20150102454A1
• Filed: 10/15/2013
• Published: 04/16/2015
• Est. Priority Date: 10/15/2013
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Khakifirooz, Ali, Reznicek, Alexander, Schepis, Dominic J.
• Granted Patent: US 9,368,492 B2
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: H01L 21/02123 the material containing silicon
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

A semiconductor substrate may be formed by providing an providing a semiconductor-on-insulator (SOI) substrate including a base semiconductor layer, a buried insulator layer above the base semiconductor layer, and a SOI layer comprising a first semiconductor material above the buried insulator layer; forming an isolation region in the SOI layer isolating a first portion of the SOI layer from a second portion of the SOI layer; removing the second portion of the SOI layer to expose a portion of the buried insulator layer; forming a hole in the exposed portion of the buried insulator layer to expose a portion of the base semiconductor layer; and forming a semiconductor layer made of a second semiconductor material on the exposed portion of the base semiconductor layer, so that the replacement semiconductor layer covers the exposed region of the buried insulator layer.

Claims

1. A method of forming a semiconductor substrate, the method comprising:

providing a semiconductor-on-insulator (SOI) substrate comprising a base semiconductor layer, a buried insulator layer above the base semiconductor layer, and a SOI layer comprising a first semiconductor material above the buried insulator layer;

forming an isolation region in the SOI layer isolating a first portion of the SOI layer from a second portion of the SOI layer;

removing the second portion of the SOI layer to expose a portion of the buried insulator layer;

forming a hole in the exposed portion of the buried insulator layer to expose a portion of the base semiconductor layer; and

forming a semiconductor layer comprising a second semiconductor material on the exposed portion of the base semiconductor layer and the exposed region of the buried insulator layer.

2. The method of claim 1, wherein the first semiconductor material is different from the second semiconductor material.

3. The method of claim 1, wherein the first semiconductor material and the second semiconductor material are selected from the group consisting of silicon, silicon-germanium, and carbon-doped silicon.

4. The method of claim 1, wherein forming a semiconductor layer comprising a second semiconductor material comprises epitaxially growing the second semiconductor material on the exposed portion of the base substrate.

5. The method of claim 4, wherein the second semiconductor material comprises the same material as the base semiconductor layer.

6. The method of claim 1, wherein forming a hole in the exposed portion of the buried insulator layer comprises etching a round hole in the buried insulator layer with a diameter of not less than approximately 10 nm.

7. The method of claim 1, wherein forming a hole in the exposed portion of the buried insulator layer comprises etching a trench with a width of not less than 10 nm in the buried insulator layer.

8. The method of claim 1, further comprising:

etching the first portion of the SOI layer to form a first fin made of the first semiconductor material; and

etching the semiconductor layer to form a second fin made of the second semiconductor material.

9. A semiconductor substrate comprising:

a base substrate layer;

a buried insulator layer above the base substrate layer;

a first semiconductor layer above the buried insulator layer;

a second semiconductor layer above the buried insulator layer approximately coplanar with the first semiconductor layer;

wherein the second semiconductor layer contacts the base substrate layer through a hole in the buried insulator layer.

10. The semiconductor substrate of claim 9, further comprising an isolation region separating the first semiconductor layer from the second semiconductor layer.

11. The semiconductor substrate of claim 9, wherein the first semiconductor layer is made of a different material than the second semiconductor layer.

12. The semiconductor substrate of claim 9, wherein the first semiconductor layer and the second semiconductor layer are made of materials selected from the group consisting of silicon, silicon-germanium, and carbon-doped silicon.

13. The semiconductor substrate of claim 9, wherein the hole is approximately round and has a diameter of no less than approximately 10 nm.

14. The semiconductor substrate of claim 9, wherein the hole is a trench having a width of no less than approximately 10 nm.

15. A semiconductor structure comprising:

a base substrate layer;

a buried insulator layer above the base substrate layer;

a first plurality of semiconductor fins on the buried insulator layer;

a second plurality of semiconductor fins on the buried insulator layer, wherein one or more of the second plurality of fins contacts the base substrate layer through a hole in the buried insulator layer.

16. The semiconductor structure of claim 15, further comprising an isolation region separating the first plurality of semiconductor fins from the second plurality of semiconductor fins.

17. The semiconductor substrate of claim 15, wherein the first plurality of semiconductor fins is made of a different material than the second plurality of semiconductor fins.

18. The semiconductor substrate of claim 17, wherein the first plurality of semiconductor fins and the second plurality of semiconductor fins are made of materials selected from the group consisting of silicon, silicon-germanium, and carbon-doped silicon.

19. The semiconductor substrate of claim 15, wherein the hole is approximately round and has a diameter of not less than approximately 10 nm.

20. The semiconductor substrate of claim 15, wherein the hole is a trench having a width, measured perpendicular to the first plurality of fins and the second plurality of fins, of a diameter of not less than approximately 10 nm.