Phase Locked Loop

• US 20150102845A1
• Filed: 10/10/2013
• Published: 04/16/2015
• Est. Priority Date: 10/10/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Tsung-Hsien
• Granted Patent: US 9,257,998 B2
• Time in Patent Office: Days
• US Class Current: 327/159
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

A circuit includes a phase locked loop and a logic IC. The phase locked loop is coupled to the logic IC. The logic IC is configured for generating an adaptive residue according to a first parameter and a second parameter. The phase locked loop is configured for providing the first parameter and the second parameter, and the phase locked loop generates an oscillator signal based on the adaptive residue.

Claims

1. A circuit, comprising:

a logic integrated circuit (IC) configured for generating an adaptive residue according to a first parameter and a second parameter; and

a phase locked loop coupled to the logic IC, the phase locked loop configured for providing the first parameter and the second parameter, the phase locked loop generating an oscillator signal based on the adaptive residue.

2. The circuit according to claim 1, wherein the phase locked loop comprises:

a phase detector;

a digital filter coupled to the phase detector; and

a digital control oscillator coupled to the digital filter, the first parameter being related to a period of the phase detector and a period of the digital control oscillator.

3. The circuit according to claim 2, wherein the second parameter is related to a frequency of the digital control oscillator and a frequency of a reference signal.

4. The circuit according to claim 3, wherein the first parameter and the second parameter are determined as follows:

5. The circuit according to claim 4, wherein the logic IC comprises:

a first multiplier coupled to the phase detector, the first multiplier configured for multiplying the first parameter and a bit number utilized by the phase locked loop to generate a first calculated value;

a calculation logic gate coupled to the digital control oscillator, the calculation logic gate configured for calculating the second parameter and a third parameter generated according to the digital filter to generate a second calculated value;

an adder coupled to the calculation logic gate, the adder configured for adding the second calculated value and a residue generated from an inverter of the phase detector to generate a third calculated value; and

a second multiplier coupled to the first multiplier and the adder, the second multiplier configured for multiplying the second calculated value and the third calculated value to generate the adaptive residue.

6. The circuit according to claim 5, wherein the adaptive residue is determined as follows:

7. A circuit, comprising:

a digital control oscillator configured for generating a first oscillator signal based on an initial residue signal;

a phase detector coupled to the digital control oscillator, the phase detector configured for comparing the first oscillator signal with a reference signal to generate the initial residue signal; and

a digital filter coupled to the phase detector, the digital filter configured for modifying the initial residue signal based on an adaptive residue related to a first parameter and a second parameter to generate a modified residue signal, the digital control oscillator configured for generating a second oscillator signal base on the modified residue signal.

8. The circuit according to claim 7, wherein the first parameter is related to a period of the phase detector and a period of the digital control oscillator.

9. The circuit according to claim 8, wherein the first parameter is determined as follows:

10. The circuit according to claim 7, wherein the second parameter is related to a frequency of the digital control oscillator and a frequency of the reference signal.

11. The circuit according to claim 10, wherein the second parameter is determined as follows:

12. The circuit according to claim 7, further comprising:

a digital processor coupled to the phase detector and the digital control oscillator, the digital processor configured for gathering information from the digital control oscillator and the phase detector to generate the first parameter and the second parameter.

13. The circuit according to claim 12, further comprising:

a logic IC coupled to the digital filter and the digital processor, the logic IC configured for calculating the first parameter and the second parameter to generate the adaptive residue.

14. The circuit according to claim 13, wherein the logic IC comprises:

a first multiplier coupled to the digital processor, the first multiplier configured for multiplying the first parameter and a bit number utilized by the phase locked loop to generate a first calculated value;

a calculation logic gate coupled to the digital processor, the calculation logic gate configured for calculating the second parameter and a third parameter generated according to the digital filter to generate a second calculated value;

an adder coupled to the calculation logic gate, the adder configured for adding the second calculated value and a residue generated from an inverter of the phase detector to generate a third calculated value; and

a second multiplier coupled to the first multiplier and the adder, the second multiplier configured for multiplying the second calculated value and the third calculated value to generate the adaptive residue.

15. The circuit according to claim 7, wherein the adaptive residue is determined as follows:

16. A method, comprising:

generating a first oscillator signal based on an initial residue signal;

comparing the first oscillator signal with a reference signal to generate the initial residue signal;

modifying the initial residue signal based on an adaptive residue related to a first parameter and a second parameter to generate a modified residue signal; and

generating a second oscillator signal base on the modified residue signal.

17. The method according to claim 16, further comprising:

generating the first parameter based on a period of a phase detector and a period of a digital control oscillator.

18. The method according to claim 16, further comprising:

generating the second parameter based on a frequency of a digital control oscillator and a frequency of the reference signal.

19. The method according to claim 16, further comprising:

calculating the first parameter and the second parameter to generate the adaptive residue.

20. The method according to claim 19, wherein the step of calculating the first parameter and the second parameter to generate the adaptive residue comprises:

multiplying the first parameter and a bit number utilized by a phase locked loop to generate a first calculated value;

calculating the second parameter and a third parameter generated according to a digital filter to generate a second calculated value;

adding the second calculated value and a residue generated from an inverter of a phase detector to generate a third calculated value; and

multiplying the second calculated value and the third calculated value to generate the adaptive residue.