Computer Processor Employing Hardware-Based Pointer Processing

• US 20150106588A1
• Filed: 10/15/2014
• Published: 04/16/2015
• Est. Priority Date: 10/15/2013
• Status: Active Grant

• Current Assignee: Mill Computing, Inc.
• Original Assignee: Mill Computing, Inc.
• Inventors: Godard, Roger Rawson, Kahlich, Arthur David
• Granted Patent: US 9,524,163 B2
• Time in Patent Office: Days
• US Class Current: 711/221
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1045 associated with a data cache
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 16/20 of structured data, e.g. relational data
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/6032 Way prediction in set-associative cache
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 2212/684 TLB miss handling
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer processor is provided with execution logic that performs operations that utilize pointers stored in memory. In one aspect, each pointer is associated with a predefined number of event bits. The execution logic processes the event bits of a given pointer in conjunction with processing a predefined pointer-related operation involving the given pointer in order to selectively output an event-of-interest signal.

In another aspect, each pointer is represented by an address field and a granularity field. The address field includes a chunk address and an offset. The granularity field represents granularity of the offset of the address field. The execution logic includes an address derivation unit that processes the granularity field of a base address for a given pointer in order to generate a valid address field for the derived pointer.

Claims

1. A computer processor comprising:

execution logic that performs operations that utilize pointers stored in a memory system operably coupled to the computer processor;

wherein each pointer is associated with a predefined number of event bits; and

wherein the execution logic is configured to process the event bits of a given pointer in conjunction with the processing of a predefined memory-related operation that involves the given pointer in order to selectively output an event-of-interest signal that provides an indication that an event-of-interest has occurred.

2. A computer processor according to claim 1, wherein:

the execution logic includes at least one mask register that corresponds to a predefined class of memory-related operations, wherein the mask register includes a number of interest bits whose values represent whether a possible event would be of interest if it did occur.

3. A computer processor according to claim 2, wherein:

the event bits of the given pointer are used to generate an index into the mask register; and

the index is used to access and select a corresponding interest bit of the mask register and then process the selected interest bit in order to selectively output the event-of-interest signal based upon the value of the selected interest bit.

4. A computer processor according to claim 1, wherein:

the execution logic includes a plurality of mask registers that correspond to different predefined classes of pointer-related operations, wherein each mask register includes a number of interest bits whose values represent whether an event-of-interest has occurred.

5. A computer processor according to claim 3, wherein:

the event bits of the given pointer are used to generate an index into a particular mask register, wherein the particular mask register corresponds to the pointer-related operation that involves the given pointer;

the index is used to access and select a corresponding interest bit of the particular mask register and then process the selected interest bit in order to selectively output the event-of-interest signal based upon the value of the selected interest bit.

6. A computer processor according to claim 1, wherein:

the execution logic includes an update interest mask register that corresponds to a predefined class of pointer-related operations that store a pointer value to memory, wherein the update interest mask register includes a number of interest bits whose values represent whether a possible event would be of interest if it did occur.

7. A computer processor according to claim 6, wherein:

the event bits of pointer address being stored to and the event bits of the pointer being stored are concatenated to generate an index into the update interest mask register, and

the index is used to access and select a corresponding interest bit of the update interest mask register and then process the selected interest bit in order to selectively output the event-of-interest signal based upon the value of the selected interest bit.

8. A computer processor according to claim 7, wherein

the event bits of the pointer address being stored to define the most-significant bits of the concatenated result that forms the index, and the event bits of the pointer value being stored define the least-significant bits of the concatenated result that forms the index.

9. A computer processor according to claim 8, wherein:

the concatenated bits of the result are treated as an integer value which forms the index.

10. A computer processor according to claim 6, wherein:

the instruction set architecture of the computer processor semantically defines the class of pointer-related operations that store a pointer value to memory in a manner that distinguishes such operations from store operations for storing an ordinary non-pointer data operand in memory.

11. A computer processor according to claim 6, wherein:

in order to support a garbage collecting scheme involve multiple regions of memory, the event bits of each respective pointer are updated to track the particular region of memory to which the respective pointer references.

12. A computer processor according to claim 1, wherein:

the execution logic includes a read interest mask register that corresponds to a predefined class of pointer-related operations that read memory through a pointer, wherein the read interest mask register includes a number of interest bits whose values represent whether a possible event would be of interest if it did occur.

13. A computer processor according to claim 1, wherein:

the execution logic includes a write interest mask register that corresponds to a predefined class of pointer-related operations that write memory through a pointer, wherein the write interest mask register includes a number of interest bits whose values represent whether a possible event would be of interest if it did occur.

14. A computer processor comprising:

execution logic that performs operations that utilize pointers stored in a memory system operably coupled to the computer processor;

wherein each pointer is represented by an address field and a granularity field, wherein address field includes a chunk address and an offset, and wherein the granularity field represents the granularity of the offset of the address field; and

wherein the execution logic includes an address derivation unit that processes the granularity field of a base address for a given pointer in order to generate a valid address field for the given pointer.

15. A computer processor according to claim 14, wherein:

the address derivation unit processes the granularity field of the base address of the given pointer to identify the offset of the address field for the given pointer.

16. A computer processor according to claim 15, wherein:

the address derivation unit checks for an offset part overflow condition in calculating the address field for the derived pointer, wherein the offset part overflow condition occurs when the address field of the derived pointer differs from the address field of the base address beyond the offset part of the derived pointer.

17. A computer processor according to claim 16, wherein:

the address derivation unit outputs a valid derived pointer address in the event that the offset part overflow condition is not detected.

18. A computer processor according to claim 16, wherein:

the address derivation unit outputs a fail signal in the event that the offset part overflow condition is detected.

19. A computer processor according to claim 14, wherein:

the instruction set architecture of the computer processor semantically defines a class of operations that utilize the address derivation unit to derive a new pointer from a given base pointer.

20. A computer processor according to claim 19, wherein:

the class of operations include pointer-increment operations and pointer-decrement operations, pointer indexing operations, pointer comparison operations, and pointer difference operations.

21. A computer processor according to claim 14, wherein:

the granularity field of a respective pointer can be updated by at least one predefined operation.

22. A computer processor according to claim 14, wherein:

the representation of a given pointer includes a valid/invalid bit that indicates whether the given pointer is valid or invalid.

23. A computer processor according to claim 22, wherein:

the address derivation unit is configured such that a derivation operation which produces a given pointer with an offset of zero and a chunk number one greater than that of the base pointer from which it is derived updates the valid/invalid bit of the given pointer to indicate that that the pointer is invalid but does not indicate an exception.

24. A computer processor according to claim 22, wherein:

the computer processor is configured such that an attempt to dereference a given pointer with a valid/invalid bit that indicates that the given pointer is invalid generates an error.

25. A computer processor according to claim 22, wherein:

the address derivation unit is configured such that a derivation operation which produces a given pointer with a chunk number one less than that of an invalid base pointer from which it is derived updates the valid/invalid bit of the given pointer to indicate that the given pointer is valid and does not indicate an exception.