Data Processing System Having Integrated Pipelined Array Data Processor

• US 20150106596A1
• Filed: 12/16/2014
• Published: 04/16/2015
• Est. Priority Date: 03/21/2003
• Status: Active Grant

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Pact XPP Technologies, AG
• Inventors: Vorbach, Martin, Weinhardt, Markus, Baumgarte, Volker, May, Frank, Becker, Jrgen
• Granted Patent: US 9,170,812 B2
• Time in Patent Office: Days
• US Class Current: 712/221
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 15/7814 Specially adapted for real time processing, e.g. comprising hardware timers
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3455 using stride
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

A data processing system having a data processing core and integrated pipelined array data processor and a buffer for storing list of algorithms for processing by the pipelined array data processor.

Claims

1. A data processing system, comprising:

a memory;

a data processor core adapted for processing software threads; and

an integrated array data processor for processing imaging algorithms;

the integrated array data processor having

i) an array of programmable arithmetic execution units,

ii) a unit for loading algorithms to the array of programmable arithmetic execution units; and

a plurality of pipeline stages for processing data; and

a joint cache shared between the data processor core and the array data processor;

the cache being connected to the memory;

the data processing system further including;

a buffer for storing a list algorithms to be loaded by the unit for loading algorithms, the list being generated by the data processor core.

2. A data processor device comprising:

a data processor core adapted for processing software threads having a plurality of data load units;

at least one array data processor having an array of programmable arithmetic execution units, the array data processor adapted for processing software threads in accordance with instruction dispatch data; and

a multi-level cache for caching instructions and data, at least one level of the multi-level cache comprising a plurality of cache slices, the multi-level cache being shared by the data processor core and the array data processor;

an instruction decoder decoding instructions so information how to process data can be provided to an instruction dispatch unit separate from the data processor core.

3. A multi-core processor comprising:

a plurality of processing units;

one 1st level instruction cache shared by the processing units;

one shared instruction fetch unit supplying the processing units jointly with instructions from the instruction cache; and

each of the processing units having;

a separate instruction fetch and decode unit; and

an execution unit path comprising a plurality of arithmetic units; and

at least one data cache being shared by the at least two processing units.

4. The multi-core processor according to claim 3, wherein the data cache comprised a hierarchy of caches, the size of at least one cache within the cache hierarchy is adaptable based on the workload.

5. The multi-core processor according to claim 4, wherein the size at least one cache is adapted by disconnecting at least one section of the cache from power supply.

6. The multi-core processor according to claim 4, wherein the size at least one cache is adapted by disconnecting at least one section of the cache from clock supply.

7. The multi-core processor according to claim 4, wherein the size at least one cache is adapted powering down at least one section of the cache.

8. The multi-core processor according to claim 4, wherein the size at least one cache is adapted by changing the power supply of at least one section of the cache

9. The multi-core processor according to claim 4, wherein at least one cache is segmented in sections.

10. The multi-core processor according to claim 3, wherein at least one of the two processing units having a dedicated 1st level data cache.

11. The multi-core processor according to the previous claim, wherein the at least one of the two processing units having a dedicated 1st level data cache sharing a higher cache level with at least one other of the at least two processing units.

12. The multi-core processor according to the previous claim, wherein one of the plurality of processing units has a dedicated 1st level data cache sharing at least the 2nd level cache with at least one other of the plurality of processing units.

13. The multi-core processor according to claim 3, wherein one of processing units comprises a floating point unit.