CONTROLLER ACCESS TO HOST MEMORY

• US 20150106660A1
• Filed: 10/16/2013
• Published: 04/16/2015
• Est. Priority Date: 10/16/2013
• Status: Abandoned Application

• Current Assignee: Lenovo Singapore Pte Limited (Lenovo Group Ltd.)
• Original Assignee: Lenovo Singapore Pte Limited (Lenovo Group Ltd.)
• Inventors: Chumbalkar, Nagananda, Waltermann, Rod D.
• Application Number:
  US14/055,743
• Publication Number:
  US 20150106660A1
• Time in Patent Office: Days
• US Class Current: 714/42
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/3006 where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems multiprogramming arrangements G06F9/46; allocation of resources G06F9/50
• CPC Class Codes: G06F 11/3055 Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction by redundancy in operation G06F11/14; error detection or correction by redundancy in hardware G06F11/16
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206
• CPC Class Codes: G06F 11/328 Computer systems status display G06F11/327 takes precedence

Abstract

An apparatus can include a circuit board; a processor mounted to the circuit board; a storage subsystem accessible by the processor; random access memory accessible by the processor; a network interface; and a controller mounted to the circuit board and operatively coupled to the network interface where the controller includes circuitry to capture values stored in the random access memory, the values being associated with a state of the apparatus, and circuitry to transmit the values via the network interface. Various other apparatuses, systems, methods, etc., are also disclosed.

Claims

1. An apparatus comprising:

a circuit board;

a processor mounted to the circuit board;

a storage subsystem accessible by the processor;

random access memory accessible by the processor;

a network interface; and

a controller mounted to the circuit board and operatively coupled to the network interface wherein the controller comprises

circuitry to capture values stored in the random access memory, the values being associated with a state of the apparatus, and

circuitry to transmit the values via the network interface.

2. The apparatus of claim 1 wherein the controller comprises circuitry to halt processing of the processor.

3. The apparatus of claim 1 wherein the controller comprises circuitry to halt a reset operation.

4. The apparatus of claim 1 wherein the controller comprises circuitry to instantiate an operational state.

5. The apparatus of claim 1 wherein the state comprises a faulty state and wherein the controller comprises circuitry to instantiate an operational state for debugging the faulty state.

6. The apparatus of claim 1 wherein the circuitry to capture values operates responsive to a trigger.

7. The apparatus of claim 6 wherein the trigger comprises a timer associated with hanging of the processor.

8. The apparatus of claim 1 comprising a component and memory for the component wherein the controller comprises circuitry to capture values stored in the memory, the values being associated with a state of the component.

9. The apparatus of claim 8 wherein the component comprises a RAID component of the storage subsystem.

10. The apparatus of claim 8 wherein the component comprises a graphics processing unit (GPU).

11. The apparatus of claim 1 wherein the network interface comprises a dedicated network interface dedicated to the controller.

12. The apparatus of claim 11 further comprising an additional network interface operatively coupled to the processor.

13. The apparatus of claim 1 wherein the random access memory comprises host memory for an operating system environment established by processing of operating system instructions by the processor.

14. The apparatus of claim 1 wherein the controller comprises memory that stores operating system instructions executable by the controller to establish a real-time operating system environment.

15. The apparatus of claim 1 wherein the processor comprises a Test Access Port (TAP) accessible by the controller.

16. The apparatus of claim 1 comprising virtualization circuitry for establishing at least one virtual machine and wherein the controller comprises association circuitry to associate an established virtual machine with values stored in the random access memory.

17. The apparatus of claim 1 wherein the controller comprises a baseboard management controller.

18. A method comprising:

providing an information handling system that comprises a processor, memory, a network interface and a controller operatively coupled to the network interface; and

receiving an instruction that instructs the controller to transmit values stored in the memory via the network interface, the values being associated with a state of the information handling system.

19. The method of claim 18 wherein receiving the instruction comprises receiving the instruction via an out-of-band communication path.

20. An apparatus comprising:

a processor;

memory operatively coupled to the processor;

a network interface; and

instructions stored in the memory and executable by the processor to instruct the apparatus to

receive, via the network interface, values, the values being stored values indicative of a faulty state of an information handling system; and

transmit, via the network interface, a debug instruction for debugging the faulty state of the information handling system based at least in part on received values, the debug instruction being executable in a real-time operating system environment to specify an operational state for the information handling system.