TRANSISTOR CHANNEL

• US 20150108430A1
• Filed: 01/06/2015
• Published: 04/23/2015
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cheng, Yu-Hung, Tsai, Ching-Wei, Tu, Yeur-Luen, Lin, Tung-I, Chen, Wei-Li
• Granted Patent: US 9,978,650 B2
• Time in Patent Office: Days
• US Class Current: 257/20
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A transistor device includes a substrate having a first region and a second region, a first semiconductor layer of a first semiconductor material having a first portion over the first region and a second portion over the second region, the first portion being separated from the second portion, a second semiconductor layer of a second semiconductor material over the second portion of the first semiconductor layer, a first transistor of a first conductivity type, the first transistor disposed within the first region and having a first set of source/drain regions formed in the first semiconductor layer, and a second transistor of a second conductivity type, the second transistor disposed within the second region and having a second set of source/drain regions formed in the second semiconductor layer. The second conductivity type is different than the second conductivity type, and the second semiconductor material is different from the first semiconductor material.

Claims

1. A transistor device comprising:

a substrate having a first region and a second region;

a first semiconductor layer of a first semiconductor material having a first portion over the first region and a second portion over the second region, the first portion being separated from the second portion;

a second semiconductor layer of a second semiconductor material over the second portion of the first semiconductor layer;

a first transistor of a first conductivity type, the first transistor disposed within the first region and having a first set of source/drain regions formed in the first semiconductor layer; and

a second transistor of a second conductivity type, the second transistor disposed within the second region and having a second set of source/drain regions formed in the second semiconductor layer;

wherein the second conductivity type is different than the second conductivity type, and the second semiconductor material is different from the first semiconductor material.

2. The device of claim 1, wherein the first semiconductor material comprises silicon germanium (SiGe) and the second semiconductor material comprises indium gallium arsenide (InGaAs).

3. The device of claim 1, further comprising, a bonding layer between the first semiconductor layer and the second semiconductor layer over the second region.

4. The device of claim 3, wherein the bonding layer comprises an oxide material.

5. The device of claim 1, wherein the first set of source/drain regions and the second set of source drain regions are epitaxially grown.

6. The device of claim 1, wherein the first set of source/drain regions comprise silicon germanium doped with boron.

7. The device of claim 1, wherein the second set of source/drain regions comprise silicon germanium doped with phosphorous.

8. The device of claim 1, wherein the first set of source/drain regions and the second set of source/drain regions comprise vertexes pointing towards a channel within respective transistors.

9. The device of claim 8, wherein tips of the vertexes of the source/drain regions are doped with a higher concentration of dopant.

10. The device of claim 9, wherein the higher concentration of dopant extends about 5 nanometers from a tip of the vertex.

11. The device of claim 8, wherein the tips of the vertexes of the source/drain regions comprise a superlattice structure.

12. The device of claim 11, wherein the superlattice structure alternates between silicon germanium and silicon, both the silicon germanium and silicon having a same type of dopant.

13. The device of claim 11, wherein sections of the superlattice structure have a thickness of about 3 nanometers.

14. The device of claim 1, wherein a thickness of the first layer in both the first feature and the second feature and a thickness of the second layer is within a range of about 50-100 nanometers.

15. A transistor device comprising:

a gate device;

a source region having a vertex pointing towards a channel beneath the gate device; and

a drain region having a vertex pointing towards the channel;

wherein a tip at the vertex of the source region and a tip at the vertex of the drain region comprise a superlattice structure.

16. The device of claim 15, wherein the superlattice structure alternates between silicon germanium and silicon in a direction that is substantially perpendicular to the substrate, both the silicon germanium and silicon having a same type of dopant.

17. The device of claim 15, wherein sections of the superlattice structure have a thickness of about 3 nanometers.

18. A method for fabricating a semiconductor device, the method comprising:

providing a first wafer comprising a substrate and a first semiconductor material layer;

bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer;

removing the sacrificial layer;

patterning the bonded wafers to create a first structure and a second structure;

removing the second semiconductor material from the first structure;

forming a first type of transistor in the first semiconductor material of the first structure; and

forming a second type of transistor in the second semiconductor material of the second structure.

19. The method of claim 18, further comprising forming a superlattice structure that alternates between two different semiconductor materials in a direction that is substantially perpendicular to the substrate, both of the semiconductor materials having a same type of dopant.

20. The method of claim 18, wherein forming the transistors comprises epitaxially growing source/drain regions within the semiconductor materials, the source/drain regions having vertexes pointed towards a region underneath a gate device.