SEMICONDUCTOR STRUCTURE WITH HIGH ENERGY DOPANT IMPLANTATION

• US 20150108568A1
• Filed: 10/21/2013
• Published: 04/23/2015
• Est. Priority Date: 10/21/2013
• Status: Abandoned Application

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: TERRILL, Kyle, GUAN, Lingpeng
• Application Number:
  US14/058,933
• Publication Number:
  US 20150108568A1
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device has an epitaxial layer grown over a substrate, each having a first dopant type. A structure disposed within the epitaxial layer has multiple trenches, each of which has a gate and a source electrode disposed within a shield oxide matrix. Multiple mesas each isolate a pair of the trenches from each other. A body region with a second dopant type is disposed above the epitaxial layer and bridges each of the mesas. A region of elevated concentration of the first dopant type is implanted at a high energy level between the epitaxial layer and the body region, which reduces resistance spreading into a channel of the device. A source region having the first dopant type is disposed above the body region.

Claims

1. A semiconductor device, comprising:

an epitaxial layer grown over a semiconductor substrate, each comprising a first type of dopant;

a structure disposed within the epitaxial layer, the structure comprising;

a plurality of trenches, each of the trenches comprising a gate electrode and a source electrode disposed within a shield oxide matrix; and

a plurality of mesas, each of which isolates a first of the plurality of trenches from a second of the plurality of trenches;

a body region bridging each of the plurality of mesas, wherein the body region is disposed above the epitaxial layer and comprises a second type of dopant;

a region of elevated concentration of the first type of dopant, which is implanted between the epitaxial layer and the body region; and

a source region comprising the first type of dopant and disposed above the body region.

2. The device as recited in claim 1 wherein, within each of the plurality of trenches, the gate electrode is disposed above the source electrode and wherein each of the plurality of trenches further comprises a inter-poly oxide, which is disposed between a lower surface of the gate electrode and an upper surface of the source electrode.

3. The device as recited in claim 1 wherein the region of elevated concentration of the first type of dopant, is implanted at a high energy level, wherein the high energy level comprises at least one of at least three hundred thousand electron Volts (300 keV), in excess of 300 keV, or between 300 keV and 1,000 keV, inclusive.

4. The device as recited in claim 1 wherein the substrate is doped with a first concentration of the first type of dopant, wherein the epitaxial layer is doped with a second concentration of the first type of dopant, and wherein the first dopant concentration exceeds the second dopant concentration.

5. The device as recited in claim 1 wherein the first type of dopant differs from the second type of dopant.

6. The device as recited in claim 1 wherein first type of dopant comprises an n-type dopant and wherein the second type of dopant comprises a p-type dopant.

7. The device as recited in claim 1 wherein first type of dopant comprises a p-type dopant and wherein the second type of dopant comprises a n-type dopant.

8. The device as recited in claim 1 wherein the semiconductor substrate comprises silicon.

9. The device as recited in claim 1 wherein the epitaxial layer comprises a first semiconducting substance and wherein one or more of the gate electrode or the source electrode comprises a second semiconducting substance.

10. The device as recited in claim 9 wherein the second semiconducting substance comprises polycrystalline silicon.

11. The device as recited in claim 1, further comprising a gate electrically coupled to the gate electrode wherein the gate is self-aligned in relation to the source region.

12. A method for fabricating a semiconductor device, the method comprising:

growing an epitaxial layer grown over a semiconductor substrate, each of which comprises a first type of dopant;

assembling a structure disposed within the epitaxial layer, the structure comprising;

a plurality of trenches, each of the trenches comprising a gate electrode and a source electrode disposed within a oxide matrix; and

a plurality of mesas, each of which isolates a first of the plurality of trenches from a second of the plurality of trenches;

depositing a body region bridging each of the plurality of mesas, wherein the body region is disposed above the epitaxial layer and comprises a second type of dopant;

implanting, between the epitaxial layer and the body region, a region of elevated concentration of the first type of dopant; and

implanting a source region, comprising the first type of dopant.

13. The method as recited in claim 12 wherein, within each of the plurality of trenches, the gate electrode is disposed above the source electrode and wherein each of the plurality of trenches further comprises a inter-poly oxide, which is disposed between a lower surface of the gate electrode and an upper surface of the source electrode.

14. The method as recited in claim 12 wherein the region of elevated concentration of the first type of dopant, is implanted at a high energy level, which and comprises at least one of at least three hundred thousand electron Volts (300 keV), in excess of 300 keV, or between 300 keV and 1,000 keV, inclusive.

15. The method as recited in claim 12 wherein the substrate is doped with a first concentration of the first type of dopant, wherein the epitaxial layer is doped with a second concentration of the first type of dopant, and wherein the first dopant concentration exceeds the second dopant concentration.

16. The method as recited in claim 12 wherein the first type of dopant differs from the second type of dopant.

17. The method as recited in claim 12 wherein first type of dopant comprises an n-type dopant and wherein the second type of dopant comprises a p-type dopant.

18. The method as recited in claim 12 wherein first type of dopant comprises a p-type dopant and wherein the second type of dopant comprises a n-type dopant

19. The method as recited in claim 12 wherein the semiconductor substrate comprises silicon.

20. The method as recited in claim 12 wherein the epitaxial layer comprises a first semiconducting substance and wherein one or more of the gate electrode or the source electrode comprises a second semiconducting substance.

21. The method as recited in claim 20 wherein the second semiconducting substance comprises polycrystalline silicon.

22. The method as recited in claim 12, further comprising installing a gate, which is self-aligned in relation to the source region and electrically coupled to the gate electrode.

23. A semiconductor device product, which is formed by a production process comprising:

growing an epitaxial layer grown over a semiconductor substrate, each of which comprises a first type of dopant;

assembling a structure disposed within the epitaxial layer, the structure comprising;

a plurality of trenches, each of the trenches comprising a gate electrode and a source electrode disposed within a oxide matrix, which fills a void etched within the epitaxial layer; and

a plurality of mesas, each of which isolates a first of the plurality of trenches from a second of the plurality of trenches;

implanting a body region bridging each of the plurality of mesas, wherein the body region is disposed above the epitaxial layer and comprises a second type of dopant;

implanting, between the epitaxial layer and the body region, a region of elevated concentration of the first type of dopant at a high energy level;

implanting a source region, comprising the first type of dopant; and

installing a gate, which is self-aligned in relation to the source region and electrically coupled to the gate electrode.