Electrically Isolated SiGe FIN Formation By Local Oxidation

• US 20150108572A1
• Filed: 10/21/2013
• Published: 04/23/2015
• Est. Priority Date: 10/21/2013
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, He, Hong, Tseng, Chiahsun, Yin, Yunpeng
• Granted Patent: US 9,093,326 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A silicon germanium alloy layer is formed on a semiconductor material layer by epitaxy. An oxygen impermeable layer is formed on the silicon germanium alloy layer. The oxygen impermeable layer and the silicon germanium alloy layer are patterned to form stacks of a silicon germanium alloy fin and an oxygen impermeable cap. A shallow trench isolation structure is formed by deposition, planarization, and recessing or an oxygen permeable dielectric material. An oxygen impermeable spacer is formed around each stack of a silicon germanium alloy fin and an oxygen impermeable cap. A thermal oxidation process is performed to convert a lower portion of each silicon germanium alloy fin into a silicon germanium oxide. During the thermal oxidation process, germanium atoms diffuse into unoxidized portions of the silicon germanium alloy fins to increase the germanium concentration therein.

Claims

1. A semiconductor structure comprising:

a semiconductor oxide material portion that contains a semiconductor oxide layer located on a semiconductor material layer and further contains a plurality of semiconductor oxide pedestals that protrudes above said semiconductor oxide layer;

a plurality of silicon germanium alloy fins located on said plurality of semiconductor oxide pedestals, wherein each of said plurality of silicon germanium alloy fins is located directly on, and above, one of said plurality of semiconductor oxide pedestals; and

a shallow trench isolation structure contacting a top surface of said semiconductor oxide layer and sidewalls of said plurality of semiconductor oxide pedestals, wherein bottommost portions of said plurality of silicon germanium alloy fins are more distal from said semiconductor oxide layer than a planar top surface of said shallow trench isolation structure is from said semiconductor oxide layer.

2. The semiconductor structure of claim 1, wherein each of said plurality of silicon germanium alloy fins comprises a pair of concave bottom surfaces that contact surfaces of said semiconductor oxide pedestal.

3. The semiconductor structure of claim 2, wherein said pair of concave surfaces is adjoined at an edge that is parallel to a pair of vertical sidewalls of one of said plurality of silicon germanium alloy fins.

4. The semiconductor structure of claim 1, wherein a portion of an interface between said semiconductor oxide layer and said semiconductor material layer protrudes downward in regions that do not underlie any of said plurality of silicon germanium alloy fins with respect to another portion of said interface in regions that underlie said plurality of silicon germanium alloy fins.

5. The semiconductor structure of claim 1, wherein said plurality of semiconductor oxide pedestals has a greater concentration of germanium atoms than said semiconductor oxide layer.

6. The semiconductor structure of claim 1, wherein a ratio of germanium atoms to silicon atoms in said plurality of silicon germanium alloy fins is greater than a ratio of germanium atoms to silicon atoms in said plurality of semiconductor oxide pedestals.

7. The semiconductor structure of claim 6, wherein said ratio of germanium atoms to silicon atoms in said plurality of semiconductor oxide pedestals is greater than a ratio of germanium atoms to silicon atoms in said semiconductor oxide layer.

8. The semiconductor structure of claim 1, wherein said semiconductor material layer is a single crystalline silicon layer.

9. The semiconductor structure of claim 8, wherein said plurality of silicon germanium alloy fins and said semiconductor material layer have an identical crystallographic structure, and have an identical spatial orientation for each crystallographic axis of said identical crystallographic structure.

10. The semiconductor structure of claim 1, further comprising a gate structure straddling said plurality of silicon germanium alloy fins and including a gate dielectric layer and a gate conductor.

11. A method of forming a semiconductor structure comprising:

forming a plurality of vertical stacks on a semiconductor material layer, each of said plurality of vertical stacks including a silicon germanium alloy fin and an oxygen impermeable cap;

forming a shallow trench isolation structure laterally surrounding lower portions of said plurality of vertical stacks, said shallow trench isolation structure comprising an oxygen permeable material;

forming an oxygen impermeable spacer directly on sidewalls of upper portions of said plurality of vertical stacks;

oxidizing an upper portion of said semiconductor material layer and lower portions of each of said plurality of silicon germanium alloy fins employing an oxidation process; and

physically exposing sidewall surfaces of remaining portions of said plurality of silicon germanium alloy fins by removing said plurality of oxygen impermeable spacers and said plurality of oxygen impermeable caps.

12. The method of claim 11, further comprising forming an oxygen permeable material layer above said shallow trench isolation structure and between said plurality of vertical stacks prior to said oxidation process.

13. The method of claim 12, further comprising removing said oxygen permeable material layer after said oxidation process.

14. The method of claim 12, wherein said oxygen permeable material layer is formed by depositing an oxygen permeable dielectric material on said shallow trench isolation structure to a height above topmost surfaces of said plurality of vertical stacks.

15. The method of claim 11, wherein said semiconductor material layer does not include germanium, or includes less germanium than said plurality of silicon germanium alloy fins.

16. The method of claim 11, wherein said oxidation process drives germanium atoms from oxidized portions of said plurality of silicon germanium alloy fins into unoxidized remaining portions of said plurality of silicon germanium alloy fins.

17. The method of claim 11, wherein said plurality of vertical stacks is formed by:

providing a material stack including a silicon germanium alloy layer and an oxygen impermeable material layer on said semiconductor material layer; and

patterning said material stack, wherein remaining portions of said material stack comprise said plurality of vertical stacks.

18. The method of claim 17, wherein said silicon germanium alloy layer is formed by epitaxial deposition of a silicon germanium alloy material on a single crystalline semiconductor material in said semiconductor material layer.

19. The method of claim 18, wherein said semiconductor material layer is a single crystalline silicon layer.

20. The method of claim 11, further comprising forming a gate structure straddling said remaining portions of said plurality of silicon germanium alloy fins, said gate structure comprising a gate dielectric and a gate electrode.