HYBRID MANGANESE AND MANGANESE NITRIDE BARRIERS FOR BACK-END-OF-LINE METALLIZATION AND METHODS FOR FABRICATING THE SAME
First Claim
1. A method for fabricating an integrated circuit comprising:
- providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material;
selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being diffusable into the conductive material at annealing temperatures;
modifying the first barrier material on the surface to form a second barrier material, the second barrier material being non-diffusable into the conductive material at annealing temperatures;
depositing a second layer of the first barrier material along the sidewalls of the opening; and
annealing the semiconductor substrate.
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Accused Products
Abstract
A method for fabricating an integrated circuit includes providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material and selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being such that, if annealed in an annealing process, the first barrier material would diffuse into the conductive material. The method further includes modifying the first barrier material on the exposed surface to form a second barrier material, the second barrier material being such that, during an annealing process, the second barrier material does not diffuse into the conductive material and depositing a second layer of the first barrier material along the sidewalls of the opening. Still further, the method includes annealing the semiconductor substrate. Integrated circuits fabricated in accordance with the foregoing method are also disclosed.
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Citations
20 Claims
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1. A method for fabricating an integrated circuit comprising:
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providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material; selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being diffusable into the conductive material at annealing temperatures; modifying the first barrier material on the surface to form a second barrier material, the second barrier material being non-diffusable into the conductive material at annealing temperatures; depositing a second layer of the first barrier material along the sidewalls of the opening; and annealing the semiconductor substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method for fabricating an integrated circuit comprising:
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providing a conductive material and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material; selectively depositing a first layer of a manganese metal barrier material on the exposed surface of the opening but not on the sidewalls of the opening; modifying the manganese barrier material on the exposed surface to form a manganese nitride barrier material; depositing a second layer of the manganese barrier material along the sidewalls of the opening; and annealing the semiconductor substrate to form a manganese silicate material along the sidewalls of the opening. - View Dependent Claims (17, 18, 19)
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20. An integrated circuit structure comprising:
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a semiconductor substrate; an electrical device overlying the semiconductor substrate; a copper metallization layer over the electrical device; a silicon oxide dielectric material layer overlying the metallization layer, the dielectric material layer having an opening therein comprising a bottom portion and sidewalls; a manganese nitride layer at the bottom portion of the opening and in abutting contact with the metallization layer; a manganese silicate layer along the sidewalls; and a copper interconnect structure filling the opening and in abutting contact with the manganese nitride layer and the manganese silicate layer.
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Specification