METHOD FOR WRITING TO A MAGNETIC TUNNEL JUNCTION DEVICE

• US 20150109854A1
• Filed: 12/23/2014
• Published: 04/23/2015
• Est. Priority Date: 11/17/2011
• Status: Active Grant

• Current Assignee: Andre Thomas, Syed M. Alam
• Original Assignee: Andre Thomas, Syed M. Alam
• Inventors: Alam, Syed M., Andre, Thomas
• Granted Patent: US 9,378,796 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods

Abstract

A method of applying a write current to a magnetic tunnel junction device minimizes sub-threshold leakage. NMOS- and PMOS-follower circuits are used in applying the write current, and bias signals for the follower circuits are isolated from global bias signals before the write current is applied.

Claims

1. A method of applying a write current through a magnetic tunnel junction device, wherein a first end of the magnetic tunnel junction device is coupled to a first electrode of a corresponding select transistor, the method comprising:

applying a first voltage to a control electrode of the select transistor to select the magnetic tunnel junction device;

applying a second voltage to a second end of the magnetic tunnel junction device using an NMOS-follower circuit; and

applying a third voltage to a second electrode of the select transistor using a PMOS-follower circuit.

2. The method of claim 1, wherein applying the second voltage to the second end of the magnetic tunnel junction device further comprises applying the second voltage to a first common line coupled to the second end of the magnetic tunnel junction device, and wherein applying the third voltage to the second electrode of the select transistor further comprises applying the third voltage to a second common line coupled to the second electrode of the select transistor.

3. The method of claim 2, wherein the first common line is a bit line, and wherein applying the second voltage further comprises selecting the bit line using a bit line select transistor.

4. The method of claim 3, wherein the second common line is a source line, and wherein applying the third voltage further comprises selecting the source line using a source line select transistor.

5. The method of claim 1, further comprising isolating a bias signal in the NMOS-follower circuit from a global bias signal before applying the second voltage.

6. The method of claim 1, wherein the NMOS-follower circuit includes a first switch transistor coupled in series with an NMOS-follower transistor, and wherein applying the second voltage includes providing a first enable signal to a control electrode of the first switch transistor.

7. The method of claim 6, wherein the NMOS-follower circuit further includes a capacitor coupled between a control electrode of the NMOS-follower transistor and a voltage supply, the method further comprising:

providing a global bias signal to the control electrode of the NMOS-follower transistor; and

isolating the global bias signal from the control electrode of the NMOS-follower transistor before applying the second voltage.

8. The method of claim 6, wherein the PMOS-follower circuit includes a second switch transistor coupled in series with a PMOS-follower transistor, and wherein applying the third voltage includes providing a second enable signal to a control electrode of the second switch transistor.

9. The method of claim 8, wherein the PMOS-follower circuit includes a capacitor coupled between a control electrode of the PMOS-follower transistor and a voltage supply, the method further comprising:

providing a global bias signal to the control electrode of the PMOS-follower transistor; and

isolating the global bias signal from the control electrode of the PMOS-follower transistor before applying the third voltage.

10. The method of claim 8, wherein the NMOS-follower circuit includes a capacitor coupled between a control electrode of the NMOS-follower transistor and a control electrode of the PMOS-follower transistor of the PMOS-follower circuit, the method further comprising:

providing a first global bias signal to the control electrode of the NMOS-follower transistor;

providing a second global bias signal to the control electrode of the PMOS-follower transistor;

isolating the first global bias signal from the control electrode of the NMOS-follower transistor before applying the second voltage; and

isolating the second global bias signal from the control electrode of the PMOS-follower transistor before applying the third voltage.

11. A method of applying a write current through a magnetic tunnel junction device, wherein a first end of the magnetic tunnel junction device is coupled to a first electrode of a corresponding select transistor, the method comprising:

applying a first voltage to a control electrode of the select transistor to select the magnetic tunnel junction device;

applying a second voltage to a second electrode of the select transistor using an NMOS-follower circuit; and

applying a third voltage to a second end of the magnetic tunnel junction device using a PMOS-follower circuit.

14. The method of claim 11, wherein the NMOS-follower circuit includes:

a switch transistor coupled in series with an NMOS-follower transistor; and

a capacitor coupled between a control electrode of the NMOS-follower transistor and a voltage supply; and

wherein the method further comprises;

providing a global bias signal to a control electrode of the NMOS-follower transistor; and

isolating the global bias signal from the control electrode of the NMOS-follower transistor before applying the second voltage.

15. The method of claim 11, wherein the PMOS-follower circuit includes:

a switch transistor coupled in series with a PMOS-follower transistor; and

a capacitor coupled between a control electrode of the PMOS-follower transistor and a voltage supply; and

wherein the method further comprises;

providing a global bias signal to a control electrode of the PMOS-follower transistor; and

isolating the global bias signal from the control electrode of the PMOS-follower transistor before applying the third voltage.

12. The method of claim 12, wherein applying the second voltage to the second electrode of the select transistor further comprises applying the second voltage to a first common line coupled to the second electrode of the select transistor, and wherein applying the third voltage to the second end of the magnetic tunnel junction device further comprises applying the third voltage to a second common line coupled to the second end of the magnetic tunnel junction device.

13. The method of claim 12, wherein the first common line is a source line and the second common line is a bit line, wherein applying the second voltage further comprises selecting the source line using a source line select transistor, and wherein applying the third voltage further comprises selecting the bit line using a bit line select transistor.

16. A method of applying a write current through a magnetic tunnel junction device, wherein a first end of the magnetic tunnel junction device is coupled to a first electrode of a corresponding select transistor, the method comprising:

providing a first global bias signal to a control electrode of an NMOS-follower transistor included in an NMOS-follower circuit, the NMOS-follower circuit including a first switch transistor coupled in series with the NMOS-follower transistor;

providing a second global bias signal to a control electrode of a PMOS-follower transistor included in a PMOS-follower circuit, the PMOS-follower circuit including a second switch transistor coupled in series with the PMOS-follower transistor;

applying a first voltage to a control electrode of the select transistor to select the magnetic tunnel junction device;

isolating the first global bias signal from the control electrode of the NMOS-follower transistor;

isolating the second global bias signal from the control electrode of the PMOS-follower transistor;

after isolating the first global bias signal from the control electrode of the NMOS-follower transistor, applying a second voltage to a second end of the magnetic tunnel junction device using the NMOS-follower circuit; and

after isolating the second global bias signal from the control electrode of the PMOS-follower transistor, applying a third voltage to a second electrode of the select transistor using the PMOS-follower circuit.

17. The method of claim 16, wherein the NMOS-follower circuit includes a first capacitor coupled between the control electrode of the NMOS-follower transistor and a first voltage supply, wherein isolating the first global bias signal further comprises using a first bias isolation transistor to isolate the control electrode of the NMOS-follower transistor from a first global bias node.

18. The method of claim 17, wherein the PMOS-follower circuit includes a second capacitor coupled between the control electrode of the PMOS-follower transistor and a second voltage supply, wherein isolating the first global bias signal further comprises using a second bias isolation transistor to isolate the control electrode of the PMOS-follower transistor from a second global bias node.

19. The method of claim 16, wherein a capacitor is coupled between the control electrode of the NMOS-follower transistor and the control electrode of the PMOS-follower transistor, wherein isolating the first global bias signal from the control electrode of the NMOS-follower transistor and isolating the second global bias signal from the control electrode of the PMOS-follower transistor includes capacitively coupling the control electrode of the NMOS-follower transistor and the control electrode of the PMOS-follower transistor.

20. The method of claim 16, wherein applying the second voltage further comprises driving a bit line using the NMOS-follower circuit, and wherein applying the third voltage further comprises driving a source line using the PMOS-follower circuit.