ROW HAMMER MONITORING BASED ON STORED ROW HAMMER THRESHOLD VALUE

• US 20150109871A1
• Filed: 12/17/2013
• Published: 04/23/2015
• Est. Priority Date: 11/30/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Kuljit Bains
• Inventors: BAINS, Kuljit, Halbert, John
• Granted Patent: US 9,384,821 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/4078 Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells protection of memory contents during checking or testing G11C29/52
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing

Abstract

Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to it row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

Claims

1. A system comprising:

a synchronous dynamic random access memory (SDRAM) device, the SDRAM device including;

a memory array having one or more rows of memory cells;

a mode register a mode register to store a Maximum Activate Count (tMAC) for the SDRAM device;

a memory controller coupled to the SDRAM device, the memory controller to include;

detection logic capable of obtaining the tMAC from the mode register, and capable of monitoring the number of activates within a maximum activate window (tMAW) for the one or more TOWS of the SDRAM device; and

command and control logic to issue an activate command (ACT) to initiate as target row refresh (TRR) mode if tMAC is exceeded.

2. The system of claim 1, wherein a row in which the tMAC is exceeded is a target row (TRn).

3. The system of claim 2, wherein the TRR mode refreshes rows adjacent to the TRn.

4. The system of claim 1, wherein the mode register further includes tMAC decode values.

5. The system of claim 2, wherein the MAC decode values include a threshold value for the SDRAM device.

6. The system of claim 4, wherein the tMAC decode values include threshold values for at least one memory device that is different from the SDRAM device.

7. The system of claim 1, wherein the SDRAM device is a DDR4 SDRAM device.

8. The system of claim 1, wherein the SDRAM device is a LPDDR4 SDRAM device.

9. A synchronous dynamic random access memory (SDRAM) device, the SDRAM device comprising:

a memory array having one or more rows of memory cells;

a mode register to hold a Maximum Activate Count (tMAC) value for the SDRAM device, and

the mode register to hold a maximum activate window (MAW) value for the SDRAM device.

10. The SDRAM device of claim 9, wherein the SDRAM device is a DDR4 SDRAM device.

11. The SDRAM device of claim 9, wherein the SDRAM device is a LPDDR4 SDRAM device.

12. A memory controller comprising:

detection logic capable of obtaining a Maximum Activate Count (tMAC) from a mode register of a synchronous dynamic random access memory (SDRAM) device , and capable of monitoring the number of activates within a maximum activate window (tMAW) for one or more rows of memory cells of the SDRAM device; and

command and control logic to issue an Activate (ACT) command to initiate, a targeted row refresh (TRR) mode if tMAC is exceeded.

13. The memory controller of claim 12, wherein the memory controller is integrated onto the same integrated circuit as a processor.

14. The memory controller of claim 12, wherein the SDRAM device is a DDR4 SDRAM device.

15. The memory controller of claim 12, wherein the SDRAM device is a LPDDR4 SDRAM device.