PROTECTION OF THE EXECUTION OF AN ALGORITHM AGAINST SIDE-CHANNEL ATTACKS

• US 20150110265A1
• Filed: 10/22/2014
• Published: 04/23/2015
• Est. Priority Date: 10/23/2013
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: Proton World International N.V. (STMicroelectronics NV)
• Inventors: Modave, Jean-Louis, Wostyn, Alexandre
• Granted Patent: US 9,565,016 B2
• Time in Patent Office: Days
• US Class Current: 380/28
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/755 with measures against power attack
• CPC Class Codes: G06F 21/77 in smart cards
• CPC Class Codes: H04L 2209/26 Testing cryptographic entity, e.g. testing integrity of encryption key or encryption algorithm
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]

Abstract

A protection mechanism for the execution of an encryption algorithm is disclosed. In the mechanism the encryption algorithm has its execution preceded by an update of a counter stored in a reprogrammable non-volatile memory. Storing the value of the counter into the memory corresponds with the execution of the algorithm.

Claims

1. A method to protect execution of an encryption algorithm, comprising:

updating a counter before execution of the encryption algorithm, the counter configured for storage in a reprogrammable non-volatile memory; and

storing a value of the counter into the non-volatile memory during execution of the encryption algorithm.

2. The method of claim 1 wherein storing the value of the counter into the non-volatile memory during execution of the encryption algorithm comprises:

activating a write function of a reprogrammable non-volatile memory;

writing a value into a counter stored in the reprogrammable non-volatile memory;

deactivating the write function of the memory; and

executing the encryption algorithm between the activating and deactivating.

3. The method of claim 2 wherein writing the value into the counter corresponds with beginning execution of the encryption algorithm.

4. The method of claim 2 wherein writing the value into the counter occurs after execution of the encryption algorithm begins.

5. The method of claim 1 wherein the encryption algorithm is an AES algorithm.

6. The method of claim 2, comprising:

analyzing power consumption of a circuit performing the activating, the writing, the executing, and the deactivating.

7. The method of claim 6 wherein analyzing the circuit power consumption includes executing a simple power analysis (SPA) or executing a differential power analysis (DPA).

8. The method of claim 1, comprising:

verifying the value is within a threshold before executing the encryption algorithm; and

prohibiting the act of executing the encryption algorithm if the value is outside of the threshold.

10. The encryption algorithm execution circuit of claim 8 wherein the processing unit is configured to begin storing the count value after beginning to execute the encryption algorithm.

11. The encryption algorithm execution circuit of claim 8 wherein the processing unit is configured to begin storing the count value and begin executing the encryption algorithm at about a same time.

12. The encryption algorithm execution circuit of claim 10 wherein a time between beginning to store the count value and beginning to execute the encryption algorithm is random.

13. The encryption algorithm execution circuit of claim 8 wherein an amount of time to complete storing the count value and an amount of time to execute the encryption algorithm is substantially equal.

14. The encryption algorithm execution circuit of claim 8 wherein the reprogrammable non-volatile memory is an EEPROM.

9. An encryption algorithm execution circuit, comprising:

a reprogrammable non-volatile memory;

a counting circuit wherein a count value produced by the counting circuit is storable in the reprogrammable non-volatile memory; and

a processing unit to execute an encryption algorithm, the processing unit configured to enable a write function in the reprogrammable non-volatile memory, concurrently execute the encryption algorithm and store a count value in the reprogrammable non-volatile memory, and disable the write function in the reprogrammable non-volatile memory.

15. A method, comprising:

activating charge pump circuits of a reprogrammable non-volatile memory;

storing a valid count value in the reprogrammable non-volatile memory; and

concurrent with the storing, executing an encryption algorithm.

16. The method of claim 15, comprising:

checking a first count value; and

based on the first count value, updating the first count value to produce the valid count value and permitting the activating, the storing, and the executing.

17. The method of claim 16, comprising:

if the first count value is outside a threshold, prohibiting the activating, the storing, and the executing.

18. The method of claim 15, comprising:

deactivating the charge pump circuits of the reprogrammable non-volatile memory.

19. The method of claim 15 wherein the encryption algorithm is an AES algorithm.

20. The method of claim 18 wherein the act of activating the charge pump circuits begins before executing the encryption algorithm and the act of deactivating the charge pump circuits ends after executing the encryption algorithm.

21. The method of claim 15 wherein the act of activating the charge pump circuits begins at a time t₁ and the act of executing the encryption algorithm begins at a time t₂ and wherein the time between t₁ and t₂ is a random time less than the time to execute the encryption algorithm.