METHODS OF DESIGNING THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) AND RELATED SYSTEMS AND COMPONENTS
First Claim
1. A non-transitory computer readable medium comprising software with instructions to:
- store a library of cells that model elements within an integrated circuit (IC), the library of cells containing cells that;
model at least one two dimensional (2D) cell for placement in an upper tier of a three dimensional (3D) IC (3DIC);
model at least one 2D cell for placement in a lower tier of the 3DIC; and
model at least one 3D cell for placement in a plurality of tiers of the 3DIC;
allow a user to select cells from the library for placement in the 3DIC such that the upper and lower tiers have identical x-y dimensions;
constrain placement of cells based on potential overlap of bottom tier elements within one or more cells; and
automatically provide a layout of conductive interconnections between placed cells.
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Abstract
Methods of designing three dimensional integrated circuits (3DIC) and related systems and components are disclosed. An exemplary embodiment provides an improved cell library for use with existing place and route software in such a manner that the modified software allows building 3DICs. The improved cell library includes 3D cells that have the footprint of the cell projected onto a two dimensional (2D) image. The projected view may then be discounted to the portion of the cell that is within an upper tier so that the cell appears to the place and route software to be a 2D cell. The discounted 2D image is then used by the place and route software. Such cells allow a circuit designer to leverage the existing 2D place and route tools as well as static timing analysis tools.
18 Citations
22 Claims
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1. A non-transitory computer readable medium comprising software with instructions to:
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store a library of cells that model elements within an integrated circuit (IC), the library of cells containing cells that; model at least one two dimensional (2D) cell for placement in an upper tier of a three dimensional (3D) IC (3DIC); model at least one 2D cell for placement in a lower tier of the 3DIC; and model at least one 3D cell for placement in a plurality of tiers of the 3DIC; allow a user to select cells from the library for placement in the 3DIC such that the upper and lower tiers have identical x-y dimensions; constrain placement of cells based on potential overlap of bottom tier elements within one or more cells; and automatically provide a layout of conductive interconnections between placed cells. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A computing device, comprising:
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a user interface having hardware elements with which a user may physically interact; memory elements; a control system operatively coupled to the memory elements and the user interface, the control system configured to; store in the memory elements a library of cells that model elements within an integrated circuit (IC), the library of cells containing cells that; model at least one two dimensional (2D) cell for placement in an upper tier of a three dimensional (3D) IC (3DIC); model at least one 2D cell for placement in a lower tier of the 3DIC; and model at least one 3D cell for placement in a plurality of tiers of the 3DIC; allow a user to select cells from the library for placement in the 3DIC such that the upper and lower tiers have identical x-y dimensions; constrain placement of cells based on potential overlap of bottom tier elements within one or more cells; and automatically provide a layout of conductive interconnections between placed cells. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A method of using a computing device loaded with place and route software to design a three dimensional (3D) integrated circuit (IC) (3DIC), comprising:
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storing a library of cells that model elements within an IC in non-transitory memory elements of the computing device, wherein cells are selected from a group of cells that; model at least one two dimensional (2D) cell for placement in an upper tier of the 3DIC; model at least one 2D cell for placement in a lower tier of the 3DIC; model at least one 3D cell for placement in a plurality of tiers of the 3DIC; allowing a user to select cells from the library for placement in the 3DIC; constraining dimensions of tiers within the 3DIC such that x-y dimensions of each tier are identical; constraining placement of cells based on potential overlap of bottom tier elements within one or more cells; automatically providing a layout of conductive interconnections between placed cells. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
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Specification