PROCESSOR COMMUNICATIONS
First Claim
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1. Processing apparatus comprising:
- a bus;
a first processor connected to the bus and configured to perform read and write operations over the bus according to a bus protocol;
a second processor arranged to execute multiple threads;
an inter-thread interconnect comprising a system of channel terminals, each operable to be used by one of the threads to perform input and output operations over a channel comprising a logical connection with another channel terminal, including being operable to perform input and output operations over a channel with another of said channel terminals used by another of said threads; and
an interface between the bus and the inter-thread interconnect, comprising a bus side implementing the bus protocol and an interconnect side having an instance of at least one channel terminal, wherein the first processor is thereby operable to communicate with a designated one of said threads via;
(i) the bus and (ii) a respective one of said channels between the channel terminal of the interface and a respective one of the channel terminals of the inter-thread interconnect used by the designated thread, the interface providing an association between read and write operations over the bus and input and output operations performed by the channel terminal of the interface.
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Abstract
A processing apparatus comprising: a bus; a first processor connected to the bus and configured to communicate over the bus according to a bus protocol; a second, multithread processor; and an inter-thread interconnect based on a system of channels. The apparatus also comprises an interface between the bus and the inter-thread interconnect, comprising a bus side implementing the bus protocol and an interconnect side for interfacing with the system of channels. The first processor is thereby operable to communicate with a designated one of said threads via the bus and a respective channel of the inter-thread interconnect.
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Citations
28 Claims
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1. Processing apparatus comprising:
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a bus; a first processor connected to the bus and configured to perform read and write operations over the bus according to a bus protocol; a second processor arranged to execute multiple threads; an inter-thread interconnect comprising a system of channel terminals, each operable to be used by one of the threads to perform input and output operations over a channel comprising a logical connection with another channel terminal, including being operable to perform input and output operations over a channel with another of said channel terminals used by another of said threads; and an interface between the bus and the inter-thread interconnect, comprising a bus side implementing the bus protocol and an interconnect side having an instance of at least one channel terminal, wherein the first processor is thereby operable to communicate with a designated one of said threads via;
(i) the bus and (ii) a respective one of said channels between the channel terminal of the interface and a respective one of the channel terminals of the inter-thread interconnect used by the designated thread, the interface providing an association between read and write operations over the bus and input and output operations performed by the channel terminal of the interface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A computer program product comprising code embodied on a computer-readable storage medium, the code comprising at least a first thread to be executed on a multi-thread processor, wherein the first thread is configured so as when executed on the multi-thread processor to provide an interface between a bus and an inter-thread interconnect of the multi-thread processor, by:
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implementing a bus protocol of the bus in the code of the first thread, and performing one or more bus transactions to communicate with a first processor over said bus using the bus protocol; and communicating with a second thread of the multi-thread processor over a channel of said inter-thread interconnect; wherein the communication with the second thread over said channel is based on the one or more transaction performed to communicate with the first processor using said bus protocol, or vice versa.
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27. A method comprising:
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using a first processor to run at least part of a respective device driver for each of one or more devices, the first processor being arranged to communicate with each device over a bus according to a bus protocol based on memory mapped addresses; using at least one respective thread of a second, multi-thread processor to provide functionality of each device to the part of the respective device driver on the first processor; and providing an interface between the bus and an interconnect of the second processor, the interconnect being operable to communicate between the threads using a system of channels; wherein the interface is provided by associating one or more memory mapped addresses of the bus with a channel of the interconnect, thus presenting the functionality of the device to the first processor as being accessible via one or more addresses on said bus, and presenting the first processor to the respective thread as being accessible over a channel of said interconnect. - View Dependent Claims (28)
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Specification