FINAL LEVEL CACHE SYSTEM AND CORRESPONDING METHODS

• US 20150113214A1
• Filed: 10/21/2014
• Published: 04/23/2015
• Est. Priority Date: 10/21/2013
• Status: Active Grant

• Current Assignee: FLC Global, Ltd.
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat
• Granted Patent: US 9,477,611 B2
• Time in Patent Office: Days
• US Class Current: 711/106
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/152 Virtualized environment, e.g. logically partitioned system
• CPC Class Codes: G06F 2212/154 Networked environment
• CPC Class Codes: G06F 2212/161 Portable computer, e.g. notebook
• CPC Class Codes: G06F 2212/171 Portable consumer electronics, e.g. mobile phone
• CPC Class Codes: G06F 2212/20 Employing a main memory using a specific memory technology
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/22 Employing cache memory using specific memory technology
• CPC Class Codes: G06F 2212/222 : Non-volatile memory
• CPC Class Codes: G06F 2212/251 : Local memory within processor subsystem
• CPC Class Codes: G06F 2212/305 : being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G06F 2212/50 : Control mechanisms for virtual memory, cache or TLB
• CPC Class Codes: G06F 2212/60 : Details of cache memory
• CPC Class Codes: G06F 2212/6022 : Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 2212/6032 : Way prediction in set-associative cache
• CPC Class Codes: G06F 2212/608 : Details relating to cache mapping
• CPC Class Codes: G06F 2212/62 : Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 3/061 : Improving I/O performance
• CPC Class Codes: G06F 3/0613 : in relation to throughput
• CPC Class Codes: G06F 3/0638 : Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0655 : Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0656 : Data buffering arrangements
• CPC Class Codes: G06F 3/0679 : Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0683 : Plurality of storage devices
• CPC Class Codes: G06F 9/4406 : Loading of operating system
• CPC Class Codes: G11C 11/40607 : Refresh operations in memory devices with an internal cache or data buffer
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data access system including a processor and a final level cache module. The processor is configured to generate a request to access a first physical address. The final level cache module includes a dynamic random access memory (DRAM), a final level cache controller, and a DRAM controller. The final level cache controller is configured to (i) receive the request from the processor, and (ii) convert the first physical address to a first virtual address. The DRAM controller is configured to (i) convert the first virtual address to a second physical address, and (ii) access the DRAM based on the second physical address.

Claims

1. A data access system comprising:

a processor configured to generate a request to access a first physical address; and

a final level cache module comprising

a dynamic random access memory,

a final level cache controller configured to (i) receive the request from the processor, and (ii) convert the first physical address to a first virtual address, and

a dynamic random access memory controller configured to (i) convert the first virtual address to a second physical address, and (ii) access the dynamic random access memory based on the second physical address.

2. The data access system of claim 1, wherein the final level cache controller is configured to perform a full set associative translation of the first physical address to the first virtual address.

3. The data access system of claim 1, further comprising a storage drive, wherein:

the storage drive is separate from the dynamic random access memory;

the second physical address is an address in the dynamic random access memory or the storage drive; and

the final level cache controller is configured to, based on the second physical address, determine whether to access the dynamic random access memory or the storage drive.

4. The data access system of claim 3, wherein the storage drive has more storage capacity than the dynamic random access memory.

5. The data access system of claim 3, wherein the storage drive has an order of magnitude more storage capacity than the dynamic random access memory.

6. The data access system of claim 3, wherein a transfer rate of data to or from the dynamic random access memory is faster than a transfer rate of data to or from the storage drive.

7. The data access system of claim 3, wherein the storage drive includes solid-state memory or a rotating storage medium.

8. The data access system of claim 3, wherein:

the storage drive includes dynamic random access memory; and

the dynamic random access memory of the storage drive has a slower data transfer rate than the dynamic random access memory of the final level cache module.

9. The data access system of claim 1, further comprising a storage drive, wherein:

the dynamic random access memory is implemented as cache and is separate from the storage drive; and

the final level cache controller is configured to (i) determine whether to access the dynamic random access memory based on the first physical address, and (ii) determine that a cache miss has occurred for the first physical address, and (iii) based on the cache miss, signal the processor that the cache miss has occurred or access the storage drive.

10. The data access system of claim 1, further comprising a storage drive, wherein:

the dynamic random access memory is implemented as cache and is separate from the storage drive;

the dynamic random access memory controller is configured to (i) determine whether to access the dynamic random access memory based on the first virtual address, and (ii) determine that a cache miss has occurred for the first virtual address, and (iii) based on the cache miss, signal the final level cache controller that the cache miss has occurred; and

the final level cache controller is configured to access the storage drive in response to the signal indicating that the cache miss has occurred.

11. The data access system of claim 1, wherein:

the dynamic random access memory is implemented as cache;

the dynamic random access memory controller is configured to (i) determine whether to access the dynamic random access memory based on the first virtual address, and (ii) determine that a cache miss has occurred for the first virtual address, and (iii) based on the cache miss, generate a first signal to indicate to the final level cache that the cache miss has occurred;

the final level cache controller is configured to, in response to the first signal, generate a second signal to indicate to the processor that the cache miss has occurred; and

the processor is configured to, in response to the second signal, access the storage drive.

12. The data access system of claim 1, further comprising a storage drive, wherein:

the storage drive is separate from the dynamic random access memory;

the processor is configured to generate the request to transfer data;

the request indicates the first physical address; and

the final level cache controller is configured to

based on the request convert the first physical address to the first virtual address, and

the final level cache controller is configured to, based on the second physical address, determine whether to transfer the data (i) between the processor and the dynamic random access memory, or (ii) between the processor and the storage drive.

13. The data access system of claim 12, further comprising an encryption device configured to encrypt the data prior to being transferred between the processor and the storage drive.

14. The data access system of claim 1, wherein the processor is configured to (i) generate a second virtual address, and (ii) convert the second virtual address to the first physical address.

15. The data access system of claim 1, wherein:

the dynamic random access memory comprises a first portion and a second portion;

the first portion is implemented as a final level cache; and

the second portion is not implemented as cache and has a lower hierarchical level than the first portion.

16. The data access system of claim 15, wherein the dynamic random access memory controller is configured to access the first portion and the second portion based on the hierarchical levels.

17. The data access system of claim 1, wherein:

the dynamic random access memory comprises a first portion and a second portion;

the first portion is implemented as virtual memory; and

the second portion is not implemented as virtual memory and has a lower hierarchical level than the first portion.

18. The data access system of claim 1, further comprising a storage drive, wherein the storage drive is separate from the dynamic random access memory, and wherein the final level cache controller is configured to:

receive a plurality of requests from the processor to transfer second data, wherein the plurality of requests indicate a first plurality of physical addresses;

convert the first plurality of physical addresses to a plurality of virtual addresses;

convert the plurality of virtual addresses to a second plurality of physical addresses, wherein some of the second plurality of physical address are in the dynamic random access memory and others of the second plurality of physical addresses are in the storage drive; and

based on the second plurality of physical addresses, determine whether to transfer the second data (i) between the processor and the dynamic random access memory, or (ii) between the processor and the storage drive.

19. The data access system of claim 1, wherein the final level cache module is implemented by only one integrated circuit.

20. The data access system of claim 1, further comprising a storage drive, wherein:

the storage drive is separate from the dynamic random access memory;

the dynamic random access memory comprises first entries;

the storage drive comprises second entries, wherein the second entries are mapped to the first entries;

the final level cache controller is configured to, based on a remaining storage capacity in one of the first entries, transfer data between the processor and one of the second entries of the storage drive; and

the one of the second entries is mapped to the one of the first entries.

21. The data access system of claim 20, wherein each entry in the dynamic random access memory is mapped to one or more entries in the storage drive.

22. The data access system of claim 20, wherein one or more entries in the dynamic random access memory are mapped to one or more entries in the storage drive.

23. The data access system of claim 1, wherein the final level cache controller is configured to store data in the dynamic random access memory based on at least one of (i) a frequency of use of the data, (ii) a priority level of the data, or (iii) whether the data is in a locked state.

45. The method of claim 23, further comprising storing data in the dynamic random access memory based on at least one of (i) a frequency of use of the data, (ii) a priority level of the data, or (iii) whether the data is in a locked state.

24. A method for accessing a dynamic random access memory of a final level cache module, the method comprising:

generating, via a processor, a request to access a first physical address;

receiving the request from the processor at a final level cache controller;

converting the first physical address to a first virtual address via the final level cache controller;

converting the first virtual address to a second physical address via a dynamic random access memory controller; and

accessing the dynamic random access memory based on the second physical address.

25. The method of claim 24, wherein converting the first physical address to the first virtual address comprises performing a full set associative translation of the first physical address to the first virtual address.

26. The method of claim 24, further comprising based on the second physical address, determining, via the final level cache controller, whether to access the dynamic random access memory or a storage drive, wherein:

the storage drive is separate from the dynamic random access memory; and

the second physical address is an address in the dynamic random access memory or the storage drive.

27. The method of claim 26, wherein the storage drive has more storage capacity than the dynamic random access memory.

28. The method of claim 26, wherein the storage drive has an order of magnitude more storage capacity than the dynamic random access memory.

29. The method of claim 26, wherein a transfer rate of data to or from the dynamic random access memory is faster than a transfer rate of data to or from the storage drive.

30. The method of claim 26, wherein the storage drive includes solid-state memory or a rotating storage medium.

31. The method of claim 26, wherein:

the storage drive includes dynamic random access memory; and

the dynamic random access memory of the storage drive has a slower data transfer rate than the dynamic random access memory of the final level cache module.

32. The method of claim 24, further comprising:

determining whether to access the dynamic random access memory based on the first physical address, wherein the dynamic random access memory is implemented as cache;

determining that a cache miss has occurred for the first physical address; and

based on the cache miss, signaling the processor that the cache miss has occurred or accessing a storage drive, wherein the storage drive is separate from the dynamic random access memory.

33. The method of claim 24, further comprising:

determining whether to access the dynamic random access memory based on the second physical address, wherein the dynamic random access memory is implemented as cache;

determining that a cache miss has occurred for the first virtual address;

based on the cache miss, signaling the final level cache controller that the cache miss has occurred; and

accessing a storage drive in response to the signal indicating that the cache miss has occurred, wherein the storage drive is separate from the dynamic random access memory.

34. The method of claim 24, further comprising:

determining whether to access the dynamic random access memory based on the second physical address, wherein the dynamic random access memory is implemented as cache;

determining, via the dynamic random access memory controller, that a cache miss has occurred for the first virtual address;

based on the cache miss, generating a first signal to indicate to the final level cache that the cache miss has occurred;

in response to the first signal, generating at the final level cache controller a second signal to indicate to the processor that the cache miss has occurred; and

in response to the second signal, accessing a storage drive, wherein the storage drive is separate from the dynamic random access memory.

35. The method of claim 24, further comprising:

generating the request to transfer data, wherein the request indicates the first physical address;

based on the request, converting the first physical address to the first virtual address; and

based on the second physical address, determining whether to transfer the data (i) between the processor and the dynamic random access memory, or (ii) between the processor and a storage drive, wherein the storage drive is separate from the dynamic random access memory.

36. The method of claim 35, further comprising encrypting the data prior to being transferred between the processor and the storage drive.

37. The method of claim 24, further comprising:

generate a second virtual address at the processor; and

converting the second virtual address to the first physical address.

38. The method of claim 24, further comprising accessing portions of the dynamic random access memory based on hierarchical levels of the portions, wherein:

the dynamic random access memory comprises a first portion and a second portion;

the first portion is implemented as a final level cache; and

the second portion is not implemented as cache and has a lower hierarchical level than the first portion.

39. The method of claim 24, further comprising accessing portions of the dynamic random access memory based on hierarchical levels of the portions, wherein:

the dynamic random access memory comprises a first portion and a second portion;

the first portion is implemented as virtual memory; and

the second portion is not implemented as virtual memory and has a lower hierarchical level than the first portion.

40. The method of claim 24, further comprising:

receiving a plurality of requests from the processor to transfer second data, wherein the plurality of requests indicate a first plurality of physical addresses;

converting the first plurality of physical addresses to a plurality of virtual addresses;

converting the plurality of virtual addresses to a second plurality of physical addresses, wherein some of the second plurality of physical address are in the dynamic random access memory and others of the second plurality of physical addresses are in a storage drive, and wherein the storage drive is separate from the dynamic random access memory; and

based on the second plurality of physical addresses, determining whether to transfer the second data (i) between the processor and the dynamic random access memory, or (ii) between the processor and the storage drive.

41. The method of claim 24, wherein the final level cache module is implemented by only one integrated circuit.

42. The method of claim 24, further comprising:

based on a remaining storage capacity in one of first entries of the dynamic random access memory, transferring data between the processor and one of second entries of a storage drive, wherein the storage drive is separate from the dynamic random access memory, and wherein the second entries are mapped to the first entries; and

the one of the second entries is mapped to the one of the first entries.

43. The method of claim 42, wherein each entry in the dynamic random access memory is mapped to one or more entries in the storage drive.

44. The method of claim 42, wherein one or more entries in the dynamic random access memory are mapped to one or more entries in the storage drive.