ENERGY-EFFICIENT MULTICORE PROCESSOR ARCHITECTURE FOR PARALLEL PROCESSING
First Claim
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1. A computer system comprising:
- multiple processor cores each having a processor core clock input and operating according to a clock signal received at the processor core clock input to execute instructions of an instruction set in synchrony with the clock signal; and
a frequency selector associated with each given processor core having a selector input for receiving at least two frequency stable clock signals, a selection input for receiving a desired frequency selection from the given processor, and a selector output for outputting one of the frequency stable clock signals to the processor clock input depending on the selection input;
wherein the instruction set includes at least one instruction executing to change the selection input of a frequency selector associated with a processor core executing the at least one instruction.
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Abstract
A multicore computer architecture provides for clock dividers on each core, the clock dividers capable of providing rapid changes in the clock frequency of the core. The clock dividers are used to reduce the clock frequency of individual cores spinning while waiting for a synchronization instruction resolution such as a lock variable. Core power demands may be decreased before and after change in dock speed to reduce power bus disruption.
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Citations
18 Claims
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1. A computer system comprising:
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multiple processor cores each having a processor core clock input and operating according to a clock signal received at the processor core clock input to execute instructions of an instruction set in synchrony with the clock signal; and a frequency selector associated with each given processor core having a selector input for receiving at least two frequency stable clock signals, a selection input for receiving a desired frequency selection from the given processor, and a selector output for outputting one of the frequency stable clock signals to the processor clock input depending on the selection input; wherein the instruction set includes at least one instruction executing to change the selection input of a frequency selector associated with a processor core executing the at least one instruction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of synchronizing multiple processor cores in a computer system having multiple processor cores each having a processor core clock input and operating according to a clock signal received at the processor core clock input to execute instructions of an instruction set in synchrony with the clock signal;
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a frequency selector associated with each given processor core having a selector input for receiving at least two frequency stable clock signals, a selection input for receiving a desired frequency selection from the given processor core, and a selector output for outputting one of the frequency stable clock signals to the processor clock input depending on the selection input; wherein the instruction set includes at least one instruction executing to change the selection input of a frequency selector associated with a processor core'"'"'s executing the at least one instruction; the method comprising the steps of; (a) providing execution of a program among the multiple processor cores, the program having synchronization points; (b) in a given processor core, spinning at the synchronization points for a period of time in a synchronization process; (c) at a beginning of the period of time, decreasing the output clock to the given processor core; and (d) at an end of the period of time, increasing the output clock of the given processor core. - View Dependent Claims (17, 18)
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Specification