SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

• US 20150115314A1
• Filed: 03/04/2013
• Published: 04/30/2015
• Est. Priority Date: 03/05/2012
• Status: Abandoned Application

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Arakawa, Kazuki, Sumitomo, Masakiyo, Matsui, Masaki, Higuchi, Yasushi, Oyama, Kazuhiro
• Application Number:
  US14/381,238
• Publication Number:
  US 20150115314A1
• Time in Patent Office: Days
• US Class Current: 257/139
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

In a semiconductor device, a trench includes a first trench that has an opening portion on a surface of a base layer, and a second trench that is communicated with the first trench and in which a distance between opposed side walls is greater than opposed side walls of the first trench and a bottom portion is located in a drift layer. A wall surface of a connecting portion of the second trench connecting to the first trench is rounded. Therefore, an occurrence of a large electrical field concentration in the vicinity of the connecting portion between the first trench and the second trench can be suppressed. Also, when electrons are supplied from a channel region to the drift layer, it is less likely that a flow direction of the electrons will be sharply changed in the vicinity of the connecting portion. Therefore, an on-state resistance can be reduced.

Claims

1. A semiconductor device comprising:

a first conductivity-type drift layer;

a second conductivity-type base layer disposed adjacent to a front surface of the drift layer;

a plurality of trenches passing through the base layer to reach the drift layer, and being extended in a predetermined direction;

a gate insulation film formed on a wall surface of each of the trenches;

a gate electrode disposed on the gate insulation film;

a first conductivity-type emitter layer disposed on a side portion of the trench in a surface layer portion of the base layer;

a second conductivity-type collector layer disposed to be separated from the emitter layer through the drift layer;

an emitter electrode electrically connected to the base layer and the emitter layer; and

a collector electrode electrically connected to the collector layer, wherein

the trench includes a first trench that has an opening portion on a surface of the base layer and a second trench that is communicated with the first trench and in which a distance between opposed side walls of the second trench is greater than a distance between opposed side walls of the first trench, and a bottom portion of the second trench is located in the drift layer, and

a wall surface of a connecting portion of the second trench connecting to the first trench is rounded.

2. The semiconductor device according to claim 1, wherein

the bottom portion of the second trench is rounded.

3. The semiconductor device according to claim 1, wherein

a side wall of the second trench between the connecting portion and the bottom portion is rounded.

4. The semiconductor device according to claim 1, wherein

the trench is disposed such that the second trench extends from the base layer to the drift layer, and the connecting portion is located in the base layer.

5. The semiconductor device according to claim 1, wherein

a portion of the drift layer contacting the second trench is formed with a pile-up layer.

6. A manufacturing method of a semiconductor device, the semiconductor device comprising:

a first conductivity-type drift layer;

a second conductivity-type base layer disposed adjacent to a front surface of the drift layer;

a plurality of trenches passing through the base layer to reach the drift layer, and being extended in a predetermined direction;

a gate insulation film formed on a wall surface of each of the trenches;

a gate electrode disposed on the gate insulation film;

a first conductivity-type emitter layer disposed on a side portion of the trench in a surface layer portion of the base layer;

a second conductivity-type collector layer disposed to be separated from the emitter layer through the drift layer;

an emitter electrode electrically connected to the base layer and the emitter layer; and

a collector electrode electrically connected to the collector layer, wherein

the trench includes a first trench that has an opening portion on a surface of the base layer and a second trench that is communicated with the first trench and in which a distance between opposed side walls of the second trench is greater than a distance between opposed side walls of the first trench, and a bottom portion of the second trench is located in the drift layer, and

a wall surface of a connecting portion of the second trench connecting to the first trench is rounded, the manufacturing method comprising;

forming the base layer adjacent to the front surface of the drift layer;

forming the first trench in the base layer by anisotropic etching;

forming a protection film on an inner wall surface of the first trench;

removing the protection film disposed on a bottom surface of the first trench;

forming the second trench that is communicated with the first trench and in which the wall surface of the connecting portion is rounded, by performing a step including isotropic etching, thereby forming the trench;

forming the gate insulation film on the inner wall surface of the trench; and

forming the gate electrode on the gate insulation film.

7. The manufacturing method of the semiconductor device according to claim 6, wherein

the forming of the second trench includes forming a third trench that is communicated with the first trench by performing an anisotropic etching, and forming the second trench by increasing a distance between opposed side walls of the third trench by performing an isotropic etching to the third trench.