Spacer Supported Lateral Channel FET

• US 20150115325A1
• Filed: 10/31/2013
• Published: 04/30/2015
• Est. Priority Date: 10/31/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Vielemeyer, Martin
• Granted Patent: US 9,324,802 B2
• Time in Patent Office: Days
• US Class Current: 257/194
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A semiconductor device includes a semiconductor material and trenches extending into the semiconductor material from a first main surface of the semiconductor material to form mesas of semiconductor material between the trenches. The device also includes a field plate in the trenches, a body region in the mesas, a source region in contact with the body region in the mesas, and a gate electrode on the first main surface of the semiconductor material and defining a lateral channel region in each of the body regions under the gate electrodes. A drain region is at the opposing main surface of the semiconductor material. The gate electrodes adjacent opposing sides of the same field plate have the same alignment with respect to that field plate. The device can be a MOSFET or HEMT. Corresponding methods of manufacture are also provided.

Claims

1. A semiconductor device, comprising:

a semiconductor material;

a plurality of trenches extending into the semiconductor material from a first main surface of the semiconductor material to form mesas of semiconductor material between the trenches;

a field plate in the trenches;

a body region in the mesas;

a source region in contact with the body region in the mesas;

a gate electrode on the first main surface of the semiconductor material and defining a lateral channel region in each of the body regions under the gate electrodes; and

a drain region at a second main surface of the semiconductor material opposing the first main surface,

wherein the gate electrodes adjacent opposing sides of the same field plate have the same alignment with respect to that field plate.

2. The semiconductor device of claim 1, wherein each of the gate electrodes has a maximum thickness measured in a direction normal to the first main surface of the semiconductor material and a width measured along the channel region, the maximum thickness of the gate electrodes being greater than the width.

3. The semiconductor device of claim 1, wherein the field plates extend above the first main surface of the semiconductor material.

4. The semiconductor device of claim 1, further comprising:

a source electrode extending into the semiconductor material in contact with the body region and the source region.

5. The semiconductor device of claim 4, wherein the source regions are adjacent the trenches, the source electrode extends between each field electrode and an adjacent one of the gate electrodes into the mesas, and wherein the body region is separated by a section of the semiconductor material between adjacent ones of the gate electrodes disposed on the same mesa, the semiconductor device further comprising:

a doped region of the same conductivity type as the source region in the section of the semiconductor material that separates the adjacent gate electrodes disposed on the same mesa.

6. The semiconductor device of claim 4, wherein the source regions are spaced apart from the trenches, the source electrode extends between adjacent ones of the gate electrodes into the mesas, and wherein the body region is continuous between the adjacent gate electrodes on the same mesa, the semiconductor device further comprising:

a doped region of the same conductivity type as the source region adjacent the trenches in each of the mesas and spaced apart from the source region by the body region in the same mesa.

7. The semiconductor device of claim 1, wherein the source regions, the lateral channel regions, the body regions and the gate electrodes extend perpendicular to the trenches.

8. A method of manufacturing a semiconductor device, the method comprising:

forming a plurality of trenches extending into a semiconductor material from a first main surface of the semiconductor material to form mesas of semiconductor material between the trenches;

disposing a trench fill material in the trenches, the trench fill material extending above the first main surface of the semiconductor material;

forming sacrificial spacers on the semiconductor material adjacent opposing sides of the trench fill material;

forming gate electrodes on the first main surface of the semiconductor material adjacent the sacrificial spacers, the gate electrodes having the same alignment with respect to the trenches, the gate electrodes defining lateral channel regions in the mesas under the gate electrodes;

removing the sacrificial spacers after formation of the gate electrodes;

forming source regions in a region of the mesas; and

forming a drain region spaced apart from the source regions.

9. The method of claim 8, wherein disposing the trench fill material in the trenches comprises:

filling the trenches with an electrically conductive material; and

recessing the mesas so that the electrically conductive material in the trenches extends above the first main surface of the semiconductor material.

10. The method of claim 8, wherein forming the sacrificial spacers comprises:

forming a material on the semiconductor material; and

anisotropically etching the material to expose the mesas, wherein at least part of the material remaining after anisotropic etching forms the sacrificial spacers.

11. The method of claim 8, wherein the semiconductor material comprises silicon, the method further comprising:

forming a body region in each of the mesas with the channel region disposed in the body region;

forming a gate oxide on the body regions for isolating the gate electrodes from the body regions; and

forming a source electrode which extends into each of the mesas in contact with the body region and the source region.

12. The method of claim 11, wherein the source regions are formed adjacent the trenches, the source electrodes extend between each field electrode and an adjacent one of the gate electrodes into the mesas, and wherein the body region is separated by a section of the semiconductor material between adjacent ones of the gate electrodes disposed on the same mesa, the method further comprising:

forming a doped region of the same conductivity type as the source region in the section of the semiconductor material that separates the adjacent gate electrodes disposed on the same mesa.

13. The method of claim 11, wherein the source regions are spaced apart from the trenches, the source electrodes extend between adjacent ones of the gate electrodes into the mesas, and wherein the body region is continuous between the adjacent gate electrodes on the same mesa, the method further comprising:

forming a doped region of the same conductivity type as the source region adjacent the trenches in each of the mesas and spaced apart from the source region by the body region in the same mesa.

14. The method of claim 11, wherein forming the source electrodes comprises:

forming a dielectric material on the semiconductor material after formation of the gate electrodes;

forming a mask with openings on the dielectric material;

etching through the dielectric material and into the mesas through the openings in the mask; and

depositing a source electrode material after removal of the mask, the source electrode material filling openings in the dielectric material and contacting the body regions and the source regions.

15. The method of claim 14, further comprising:

forming a further dielectric material on the gate electrodes before deposition of the source electrode material.

16. The method of claim 8, wherein forming the gate electrodes comprises:

forming an electrically conductive material on the semiconductor material after formation of the sacrificial spacers; and

anisotropically etching the electrically conductive material to form the gate electrodes, wherein a width of the gate electrodes as measured in a direction along the lateral channel regions corresponds to a maximum thickness of the electrically conductive material prior to etching.

17. The method of claim 8, wherein the semiconductor material comprises silicon, the method further comprising:

implanting dopants of a first conductivity type through an opening in a mask into the mesas prior to formation of the gate electrodes to form spaced apart implanted body regions; and

implanting dopants of a second conductivity type opposite the first type into the mesas between the gate electrodes and the trenches to form implanted source regions disposed adjacent the trenches and between the spaced apart implanted body regions.

18. The method of claim 8, wherein the semiconductor material comprises III-nitride material and the channel region is formed by a two-dimensional charge carrier gas, and wherein forming the sacrificial spacers comprises:

forming a hardmask with openings on the III-nitride material;

forming contact regions in the III-nitride material through the openings in the hardmask;

forming a dielectric material along sidewalls of the openings in the hardmask;

etching the III-nitride material in a region unprotected by the hardmask and the dielectric material along the sidewalls of the openings in the hardmask, to remove at least some of the contact regions unprotected by the dielectric material;

filling the openings in the hardmask and the etched part of the III-nitride material with an electrically conductive material so that the electrically conductive material extends above the main surface of the III-nitride material;

removing the hardmask and the dielectric material along the sidewalls of the openings in the hardmask to expose sides of the electrically conductive material above the main surface of the III-nitride material; and

forming the sacrificial spacers adjacent the exposed sides of the electrically conductive material.

19. The method of claim 8, wherein the semiconductor material comprises III-nitride material and the channel region is formed by a two-dimensional charge carrier gas, and wherein forming the sacrificial spacers comprises:

forming electrodes in contact with the III-nitride material, the electrodes extending above the main surface of the III-nitride material; and

forming the sacrificial spacers adjacent exposed sides of the electrodes.

20. The method of claim 19, wherein forming the gate electrodes comprises:

depositing a gate electrode material on the III-nitride material and the sacrificial spacers; and

anisotropically etching the gate electrode material so that the gate electrode material remains only along lateral sides of the sacrificial spacers.

21. The method of claim 19, further comprising:

recessing the gate electrodes;

forming a dielectric material on the recessed gate electrodes; and

forming a field plate above and isolated from the recessed gate electrodes of each mesa by the dielectric material formed on the recessed gate electrodes.

22. A semiconductor device, comprising:

a III-nitride semiconductor material;

a plurality of trenches extending into the III-nitride semiconductor material from a first main surface of the semiconductor material to form mesas of III-nitride semiconductor material between the trenches;

a source region in each of the mesas;

a lateral two-dimensional charge carrier gas channel region adjacent the source region in the mesas;

a gate electrode on the first main surface of the semiconductor material over the lateral channel region in the mesas; and

a drain region,

wherein the gate electrodes adjacent opposing sides of the same field plate have the same alignment with respect to that field plate.

23. The semiconductor device of claim 22, wherein each of the gate electrodes has a maximum thickness measured in a direction normal to the first main surface of the semiconductor material and a width measured along the channel region, the maximum thickness of the gate electrodes being greater than the width.

24. The semiconductor device of claim 22, further comprising:

a source electrode extending between adjacent gate electrodes and into the source region of each mesa, the source electrodes being isolated from the gate electrodes; and

a field plate connected to the source electrodes and extending over the gate electrodes, the field plates being isolated from the gate electrodes.