SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

• US 20150115375A1
• Filed: 10/01/2014
• Published: 04/30/2015
• Est. Priority Date: 10/24/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoo, Jae-Hyun
• Granted Patent: US 9,508,820 B2
• Time in Patent Office: Days
• US Class Current: 257/411
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

A semiconductor device includes a gate insulation layer pattern, a lower gate electrode, an upper gate electrode, and a first inner spacer. The gate insulation layer pattern is formed on a substrate. The lower gate electrode is formed on the gate insulation layer pattern. The upper gate electrode is formed on the lower gate electrode and has a width that gradually increases from a bottom portion toward a top portion thereof. The width of the bottom portion of the upper gate electrode is smaller than a width of a top surface of the lower gate electrode. The first inner spacer surrounds a sidewall of the upper gate electrode.

Claims

1. A semiconductor device, comprising:

a gate insulation layer pattern on a substrate;

a lower gate electrode on the gate insulation layer pattern;

an upper gate electrode on the lower gate electrode, the upper gate electrode having a width that gradually increases from a bottom portion toward a top portion thereof, the width of the bottom portion of the upper gate electrode being smaller than a width of a top surface of the lower gate electrode; and

a spacer on a sidewall of the upper gate electrode.

2. The semiconductor device of claim 1, further comprising a high-k dielectric layer pattern on the gate insulation layer pattern, the high-k dielectric layer pattern surrounding a bottom and a sidewall of the lower gate electrode.

3. The semiconductor device of claim 2,

wherein the spacer comprises a first inner spacer,

wherein the semiconductor device further comprises a second inner spacer on the gate insulation layer pattern, and

wherein the second inner spacer is on an outer sidewall of the high-k dielectric layer pattern.

4. The semiconductor device of claim 2, wherein the width of the top portion of the upper gate electrode is substantially equally wide as a width of a bottom portion of the high-k dielectric layer pattern.

5. The semiconductor device of claim 1, wherein the width of the top surface of the lower gate electrode is substantially equally wide as the width of the top portion of the upper gate electrode.

6. The semiconductor device of claim 1, wherein the spacer includes a low-k dielectric material.

7. The semiconductor device of claim 1, further comprising:

an outer spacer on a sidewall of the semiconductor device;

a metal silicide pattern on the substrate adjacent the outer spacer; and

a contact plug contacting the metal silicide pattern, the contact plug including a metal, a metal nitride, or a doped polysilicon.

8. The semiconductor device of claim 1, wherein the lower gate electrode is a single layer that is uniformly wide or substantially uniformly wide from a bottom surface of the lower gate electrode to the top surface of the lower gate electrode.

9. A method of manufacturing a semiconductor device, the method comprising:

forming a gate insulation layer pattern on a substrate;

forming a lower gate electrode on the gate insulation layer pattern;

forming a spacer partially covering a top surface of the lower gate electrode; and

forming an upper gate electrode on the lower gate electrode to fill a space defined by the top surface of the lower gate electrode and the spacer, the upper gate electrode having a width that gradually increases from a bottom portion toward a top portion thereof, and the width of the bottom portion of the upper gate electrode being smaller than a width of the top surface of the lower gate electrode.

10. The method of claim 9, wherein forming the lower gate electrode comprises:

forming a dummy gate electrode on the gate insulation layer pattern to define a dummy gate structure including the gate insulation layer pattern and the dummy gate electrode;

forming an insulating interlayer on a sidewall of the dummy gate structure;

removing the dummy gate electrode to form an opening exposing the gate insulation layer pattern;

forming a high-k dielectric layer on the exposed gate insulation layer pattern, a sidewall of the opening, and the insulating interlayer;

forming a gate electrode layer on the high-k dielectric layer to fill a remaining portion of the opening;

planarizing the gate electrode layer and the high-k dielectric layer until a top surface of the insulating interlayer is exposed to form a preliminary gate electrode and a preliminary high-k dielectric layer pattern filling the opening; and

partially removing the preliminary gate electrode and the preliminary high-k dielectric layer pattern to form the lower gate electrode and a high-k dielectric layer pattern surrounding a bottom and a sidewall of the lower gate electrode.

11. The method of claim 10,

wherein forming the spacer comprises forming a first inner spacer,

wherein the method further comprises, before forming the high-k dielectric layer:

forming an inner spacer layer on the exposed gate insulation layer pattern, the sidewall of the opening, and the insulating interlayer by an atomic layer deposition (ALD) process; and

anisotropically etching the inner spacer layer to form a preliminary inner spacer on the sidewall of the opening, and

wherein forming the lower gate electrode and the high-k dielectric layer pattern further comprises partially removing the preliminary inner spacer to form a second inner spacer on a sidewall of the high-k dielectric layer pattern.

12. The method of claim 9, wherein forming the lower gate electrode comprises:

forming a preliminary gate electrode on the gate insulation layer pattern; and

removing an upper portion of the preliminary gate electrode to form the lower gate electrode.

13. The method of claim 9, further comprising forming an insulating interlayer on the substrate, the insulating interlayer comprising a recess exposing a top surface of the lower gate electrode, wherein forming the spacer and forming the upper gate electrode comprises:

forming a spacer layer on the exposed top surface of the lower gate electrode, a sidewall of the recess, and the insulating interlayer;

anisotropically etching the spacer layer to form the spacer on the sidewall of the recess, the spacer partially covering the exposed top surface of the lower gate electrode; and

forming the upper gate electrode on the exposed top surface of the lower gate electrode to fill a remaining portion of the recess.

14. A semiconductor device, comprising:

a gate insulation layer pattern on a substrate and an isolation layer, the substrate including an active region and a field region;

a lower gate electrode on the gate insulation layer pattern, the lower gate electrode including;

a first portion on at least the active region of the substrate; and

a second portion on the field region of the substrate, the second portion being connected to the first portion and having a first width that is wider than a second width of the first portion;

a spacer layer covering a top surface of the first portion of the lower gate electrode;

an upper gate electrode on the second portion of the lower gate electrode, the upper gate electrode having a width that gradually increases from a bottom portion toward a top portion thereof, and the width of the bottom portion of the upper gate electrode being narrower than a width of a top surface of the second portion of the lower gate electrode; and

a spacer surrounding a sidewall of the upper gate electrode and contacting the spacer layer.

15. The semiconductor device of claim 14, further comprising a high-k dielectric layer pattern on the gate insulation layer pattern, the high-k dielectric layer pattern surrounding a bottom and a sidewall of the lower gate electrode.