SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
First Claim
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1. A semiconductor device, comprising:
- a gate insulation layer pattern on a substrate;
a lower gate electrode on the gate insulation layer pattern;
an upper gate electrode on the lower gate electrode, the upper gate electrode having a width that gradually increases from a bottom portion toward a top portion thereof, the width of the bottom portion of the upper gate electrode being smaller than a width of a top surface of the lower gate electrode; and
a spacer on a sidewall of the upper gate electrode.
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Abstract
A semiconductor device includes a gate insulation layer pattern, a lower gate electrode, an upper gate electrode, and a first inner spacer. The gate insulation layer pattern is formed on a substrate. The lower gate electrode is formed on the gate insulation layer pattern. The upper gate electrode is formed on the lower gate electrode and has a width that gradually increases from a bottom portion toward a top portion thereof. The width of the bottom portion of the upper gate electrode is smaller than a width of a top surface of the lower gate electrode. The first inner spacer surrounds a sidewall of the upper gate electrode.
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Citations
15 Claims
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1. A semiconductor device, comprising:
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a gate insulation layer pattern on a substrate; a lower gate electrode on the gate insulation layer pattern; an upper gate electrode on the lower gate electrode, the upper gate electrode having a width that gradually increases from a bottom portion toward a top portion thereof, the width of the bottom portion of the upper gate electrode being smaller than a width of a top surface of the lower gate electrode; and a spacer on a sidewall of the upper gate electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of manufacturing a semiconductor device, the method comprising:
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forming a gate insulation layer pattern on a substrate; forming a lower gate electrode on the gate insulation layer pattern; forming a spacer partially covering a top surface of the lower gate electrode; and forming an upper gate electrode on the lower gate electrode to fill a space defined by the top surface of the lower gate electrode and the spacer, the upper gate electrode having a width that gradually increases from a bottom portion toward a top portion thereof, and the width of the bottom portion of the upper gate electrode being smaller than a width of the top surface of the lower gate electrode. - View Dependent Claims (10, 11, 12, 13)
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14. A semiconductor device, comprising:
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a gate insulation layer pattern on a substrate and an isolation layer, the substrate including an active region and a field region; a lower gate electrode on the gate insulation layer pattern, the lower gate electrode including; a first portion on at least the active region of the substrate; and a second portion on the field region of the substrate, the second portion being connected to the first portion and having a first width that is wider than a second width of the first portion; a spacer layer covering a top surface of the first portion of the lower gate electrode; an upper gate electrode on the second portion of the lower gate electrode, the upper gate electrode having a width that gradually increases from a bottom portion toward a top portion thereof, and the width of the bottom portion of the upper gate electrode being narrower than a width of a top surface of the second portion of the lower gate electrode; and a spacer surrounding a sidewall of the upper gate electrode and contacting the spacer layer. - View Dependent Claims (15)
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Specification