Semiconductor Devices, Methods of Manufacturing Thereof, and Image Sensor Devices

• US 20150115389A1
• Filed: 07/08/2014
• Published: 04/30/2015
• Est. Priority Date: 10/25/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Chun-Chieh, Yaung, Dun-Nian, Hung, Feng-Chi, Kao, Min-Feng, Lin, Jeng-Shyan, Su, Chun-Ming, Wang, Ching-Chun
• Granted Patent: US 9,391,114 B2
• Time in Patent Office: Days
• US Class Current: 257/460
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device includes a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. A guard structure is disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region. A portion of the guard structure is disposed within a substrate of the semiconductor chip.

Claims

1. A semiconductor device, comprising:

a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein; and

a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region, wherein a portion of the guard structure is disposed within a substrate of the semiconductor chip.

2. The semiconductor device according to claim 1, wherein the portion of the guard structure comprises a first portion, and wherein the guard structure includes a second portion disposed in an inter-metal dielectric (IMD) of the semiconductor chip.

3. The semiconductor device according to claim 2, wherein the second portion of the guard structure comprises a conductive via, a conductive via bar, a conductive line, or a conductive line segment.

4. The semiconductor device according to claim 2, wherein the second portion of the guard structure comprises a stack of a plurality of conductive vias or conductive via bars and a plurality of conductive lines or conductive line segments.

5. The semiconductor device according to claim 4, wherein the semiconductor chip comprises a first semiconductor chip, wherein the semiconductor device further comprises a second semiconductor chip bonded to the first semiconductor chip, wherein the guard structure includes a third portion coupled to the second portion, wherein the third portion is disposed in an IMD of the second semiconductor chip, and wherein the third portion comprises a stack of one or more conductive vias or conductive via bars, or one or more conductive lines or conductive line segments.

6. The semiconductor device according to claim 2, wherein the second portion of the guard structure comprises a metal stack.

7. The semiconductor device according to claim 2, wherein the first portion of the guard structure comprises a metal feature, an N-type region, a P-type region, or a combination thereof.

8. The semiconductor device according to claim 2, wherein the semiconductor chip comprises a plurality of the through-vias;

wherein the semiconductor chip comprises a plurality of periphery devices in the periphery region; and

wherein the guard structure is disposed proximate or around the array region, disposed proximate or around the plurality of through-vias, disposed proximate or around the plurality of through-vias and the array region, disposed proximate or around one of the plurality of through-vias, disposed proximate or around a group of the plurality of through-vias, disposed proximate or around one of the plurality of periphery devices, disposed proximate or around a group of the plurality of periphery devices, or a combination thereof.

9. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein; and

forming a guard structure in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region, wherein forming the guard structure comprises forming a first portion of the guard structure in a substrate of the semiconductor chip, and forming a second portion of the guard structure in an inter-metal dielectric (IMD) of the semiconductor chip, the second portion of the guard structure being coupled to the first portion of the guard structure.

10. The method according to claim 9, wherein forming the second portion of the guard structure comprises forming a plurality of conductive vias or conductive via bars and a plurality of conductive lines or conductive line segments, and wherein each one of the plurality of conductive lines or conductive line segments has a greater width than a width of an adjacent one of the plurality of conductive vias or conductive via bars.

11. The method according to claim 10, wherein forming the second portion of the guard structure comprises forming one of the plurality of conductive vias or conductive via bars between each two adjacent ones of the plurality of conductive lines or conductive line segments, or forming one of the plurality of conductive vias or conductive via bars between one of the plurality of conductive lines or conductive line segments and the first portion of the guard structure.

12. The method according to claim 9, wherein providing the semiconductor chip comprises providing a complementary metal oxide semiconductor (CMOS) back side illumination (BSI) image sensor device.

13. The method according to claim 9, wherein forming the guard structure comprises forming a guard structure substantially comprising a shape in a top view of the semiconductor chip selected from the group consisting essentially of:

a square, a rectangle, a continuous bar, a plurality of continuous bars, a non-continuous bar, a plurality of non-continuous bars, and combinations thereof.

14. The method according to claim 9, wherein forming the first portion of the guard structure comprises implanting the substrate of the semiconductor chip and/or epitaxially growing a material on the substrate of the semiconductor chip to form a P-type material, an N-type material, or a combination thereof.

15. The method according to claim 9, wherein forming the first portion of the guard structure comprises forming a trench in the substrate of the semiconductor chip, and filling the trench with a material.

16. The method according to claim 15, wherein filling the trench with the material comprises filling the trench with an insulating material, a conductive material, or a combination thereof.

17. The method according to claim 16, wherein filling the trench with the conductive material comprises filling the trench with a material selected from the group consisting essentially of:

W, Cu, AlCu, and combinations thereof.

18. An image sensor device, comprising:

a first semiconductor chip comprising an array region, a periphery region disposed around the array region, and a first through-via disposed between the array region and the periphery region;

a second semiconductor chip bonded to the first semiconductor chip, the second semiconductor chip comprising a second through-via disposed therein, the second through-via also being disposed in the first semiconductor chip; and

a guard structure disposed in the first semiconductor chip between the array region and the first through-via or the second through-via, or between a portion of the periphery region and the first through-via or the second through-via, wherein the guard structure comprises a first portion comprising a metal feature, an N-type region, a P-type region, or a combination thereof, and wherein the guard structure comprises a second portion comprising a metal stack.

19. The device according to claim 18, further comprising a first guard structure disposed in the first semiconductor chip between the array region and the first through-via or the second through-via, and a second guard structure disposed in the first semiconductor chip between a portion of the periphery region and the first through-via or the second through-via.

20. The device according to claim 18, wherein the image sensor device comprises a stacked complementary metal oxide semiconductor (CMOS) back side illumination (BSI) image sensor device.