ALIGNMENT TESTING FOR TIERED SEMICONDUCTOR STRUCTURE

• US 20150115986A1
• Filed: 10/25/2013
• Published: 04/30/2015
• Est. Priority Date: 10/25/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Mill-Jer, Chen, Hao, Peng, Ching-Nen, Lin, Hung-Chih, Lee, Mincent
• Granted Patent: US 9,658,281 B2
• Time in Patent Office: Days
• US Class Current: 324/750.3
• CPC Class Codes: G01B 2210/56 Measuring geometric parameters of semiconductor structures, e.g. profile, critical dimensions or trench depth
• CPC Class Codes: G01B 7/12 for measuring diameters
• CPC Class Codes: G01R 31/2601 Apparatus or methods therefor G01R31/2607, G01R31/2642 take precedence
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2891 related to sensing or controlling of force, position, temperature G01R31/2874 takes precedence; sensing of force G01L; sensing of position G01B, G01D; sensing of temperature G01K; controlling in general G05
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls
• CPC Class Codes: G01R 31/54 Testing for continuity
• CPC Class Codes: G01R 31/66 Testing of connections, e.g. of plugs or non-disconnectable joints testing for incorrect line connections G01R31/55

Abstract

Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.

Claims

1. A method for evaluating a tiered semiconductor structure, comprising:

evaluating connectivity between a first set of vias within a first layer of a tiered semiconductor structure and a second set of vias within a second layer of the tiered semiconductor structure to determine a via connection count corresponding to a number of via connections that pass a connectivity test;

determining a first via diameter based upon the via connection count;

determining a first offset based upon an offset measurement between a target design via and a measured center via, the first offset comprising an offset distance and an offset direction; and

evaluating the tiered semiconductor structure for misalignment based upon the first via diameter and the first offset.

2. The method of claim 1, the first via diameter and the first offset corresponding to a first alignment direction, and the method comprising:

determining a second via diameter and a second offset based upon evaluating connectivity utilizing a second connectivity test in a second alignment direction; and

evaluating the tiered semiconductor structure for misalignment in the second alignment direction based upon the second via diameter and the second offset.

3. The method of claim 1, the second set of vias formed as a conductive arc comprising a notch with a notch angle, and the method comprising:

responsive to determining that a first via has connectivity through the conductive arc to a third via and that the first via does not have connectivity to a second via positioned between the first via and the third via, determining an alignment rotation having a rotational value less than the notch angle; and

evaluating the tiered semiconductor structure for misalignment based upon the alignment rotation.

4. The method of claim 1, the second set of vias formed as a conductive arc comprising a notch with a notch angle, and the method comprising:

responsive to determining that a first via has connectivity through the conductive arc to a second via adjacent to the first via and that the first via does not have connectivity to a third via adjacent to the second via, determining an alignment rotation having a counterclockwise rotation value between half the notch angle and the notch angle; and

evaluating the tiered semiconductor structure for misalignment based upon the alignment rotation.

5. The method of claim 1, the second set of vias formed as a conductive arc comprising a notch with a notch angle, and the method comprising:

responsive to determining that a third via has connectivity through the conductive arc to a second via adjacent to the third via and that a first via does not have connectivity to the third via, determining an alignment rotation having a clockwise rotation value between half the notch angle and the notch angle; and

evaluating the tiered semiconductor structure for misalignment based upon the alignment rotation.

6. The method of claim 1, the second set of vias formed as a conductive arc comprising a notch with a notch angle, and the method comprising:

responsive to determining that the conductive arc provides connectivity between a first via, a second via, and a third via, determining an alignment rotation having a rotation value greater than the notch angle; and

evaluating the tiered semiconductor structure for misalignment based upon the alignment rotation.

7. The method of claim 1, the second set of vias formed as a set of conductive patterns where a pattern is formed as a conductive arc comprising a notch with a notch angle, and the method comprising:

responsive to determining that a first via has connectivity through a conductive pattern within the set of conductive patterns to a third via and that the first via does not have connectivity to a second via positioned between the first via and the third via, determining an alignment rotation having a rotational value corresponding to a notch offset angle of the conductive pattern; and

evaluating the tiered semiconductor structure for misalignment based upon the alignment rotation.

8. The method of claim 1, comprising:

evaluating the tiered semiconductor structure for misalignment during a CMOS stacking process of one or more tiers of the tiered semiconductor structure.

9. The method of claim 1, comprising:

forming a test structure within the tiered semiconductor structure as an alignment mark for prober alignment.

10. The method of claim 1, comprising:

forming a test structure within the tiered semiconductor structure for testing, the test structure deposited in at least one of a wafer edge, a scribe line, or within a device of the tiered semiconductor structure.

11. The method of claim 1, comprising:

transmitting a testing signal to perform the connectivity test utilizing at least one of a contact probe, a contactless coupling, or a probe coupling hybrid, the test signal transmitted from a source separated from a test structure.

12. The method of claim 1, comprising:

transmitting a testing signal utilizing at least one of;

a direct testing signal from automatic test equipment (ATE);

or

a testing trigger created by a built in self testing engine (BIST) employed by the ATE.

13. The method of claim 7, comprising:

forming the set of conductive patterns as a matrix of test structures.

14. The method of claim 1, comprising:

invoking at least one of a testing unit, a repair unit, or a fault tolerance unit of a testing tier to process one or more tiers during stacked CMOS production processing of the tiered semiconductor structure.

15. A system for evaluating a tiered semiconductor structure, comprising:

an alignment tester component configured to;

evaluate connectivity between a first set of vias within a first layer of a tiered semiconductor structure and a second set of vias within a second layer of the tiered semiconductor structure to determine a first via diameter and a first offset based upon a first connectivity test in a first alignment direction; and

evaluate the tiered semiconductor structure for misalignment based upon the first via diameter and the first offset.

16. The system of claim 15, the alignment tester component configured to:

determine a second via diameter and a second offset based upon evaluating connectivity utilizing a second connectivity test in a second alignment direction; and

evaluate the tiered semiconductor structure for misalignment in the second alignment direction based upon the second via diameter and the second offset.

17. The system of claim 15, the alignment tester component configured to:

invoke at least one of a testing unit, a repair unit, or a fault tolerance unit of a testing tier to process one or more tiers during stacked CMOS production processing of the tiered semiconductor structure.

18. The system of claim 15, the alignment tester component configured to test alignment during at least one of:

a first partial test wafer stage between a wafer fabrication stage and a wafer bonding stage;

a first known good die (KGD) test stage between the wafer bonding stage and a KGD bonding stage;

a partial known good stack (KGS) test stage during the KGD bonding stage;

or

a full KGS test stage after the KGD bonding stage.

19. A system for evaluating a tiered semiconductor structure, comprising:

an alignment tester component configured to;

evaluate connectivity, through a conductive arc within a second layer of a tiered semiconductor structure, between a first via, a second via, and a third via of a first layer of the tiered semiconductor structure to determine an alignment rotation; and

evaluate the tiered semiconductor structure for misalignment based upon the alignment rotation.

20. The system of claim 19, the alignment tester component configured to:

evaluate the first via, the second via, and the third via against a set of conductive patterns to determine multi-dimensional alignment rotation; and

evaluate the tiered semiconductor structure for misalignment based upon the multi-dimensional alignment rotation.