Digital Voltage Ramp Generator

• US 20150116012A1
• Filed: 10/30/2013
• Published: 04/30/2015
• Est. Priority Date: 10/30/2013
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lakdawala, Hasnain, Degani, Ofir, Ravi, Ashoke, Gordon, Eshel, Brown, Thomas W.
• Application Number:
  US14/066,961
• Publication Number:
  US 20150116012A1
• Time in Patent Office: Days
• US Class Current: 327/136
• CPC Class Codes: H03K 4/12 in which a sawtooth voltage is produced across a capacitor
• CPC Class Codes: H03K 4/48 using as active elements semiconductor devices H03K4/787 - H03K4/84 take precedence
• CPC Class Codes: H03K 4/502 the capacitor being charged from a constant-current source

Abstract

According to some embodiments, an all digital ramp generator may use a string of series connected delays or digital to time-based circuits to perform voltage ramp generation. Thus in some embodiments conventional operational amplifier circuits and relaxation oscillators may be replaced for generating triangular ramp waveforms for DC to DC or direct time-based DC to DC converters. The use of delay lines may produce sufficient resolution for many applications. Thus time domain techniques may afford a more digital approach that scales with process technology and allows high speed operation in some embodiments. A design based on use of inverters and capacitors may scale well with process technology. The decoder and drive logic may be integrated into the voltage ramp generation in some embodiments.

Claims

1. An apparatus comprising:

a digital delay line; and

a digital capacitor summing network coupled to said delay line to output a ramp waveform.

2. The apparatus of claim 1 wherein said delay line is a ring oscillator.

3. The apparatus of claim 1 wherein said delay line is an interpolated delay line.

4. The apparatus of claim 1 wherein said delay line is part of a phase locked loop or a delay locked loop.

5. The apparatus of claim 1 wherein said delay line includes an inverter string having a number of inverters and a circuit to tune the delay.

6. The apparatus of claim 5 said circuit to change the number of inverters.

7. The apparatus of claim 1 including at least two parallel connected ramp generators and a fractional delay cell.

8. The apparatus of claim 1 including a comparator coupled to said capacitor summing network.

9. The apparatus of claim 1 including a tuning circuit coupled to an input to said delay line, said circuit to adapt the input to account for process variations in said network.

10. The apparatus of claim 1 including a precharged network.

11. The apparatus of claim 10 including a binary weighting scheme.

12. The apparatus of claim 1 including an antenna, touch screen and an applications processor.

13. A method comprising:

generating a plurality of delayed outputs;

using a capacitor summing network to sum said outputs; and

generating a ramp waveform from said summed outputs.

14. The method of claim 13 including using a ring oscillator to generate said outputs.

15. The method of claim 13 including using an interpolated delay line to generate said outputs.

16. The method of claim 13 including tuning the delay.

17. The method of claim 16 including tuning the delay by changing a number of inverters in an interpolated delay line.

18. The method of claim 16 including using a tuning circuit coupled to an input to said delay line, to adapt the input to account for process variations in said network.

19. The method of claim 13 including using at least two parallel connected ramp generators and a fractional delay cell.

20. The method of claim 13 including precharging the capacitor summing network.

21. An apparatus comprising:

a device including an interpolated delay line or a ring oscillator; and

a capacitive summing network coupled to said device.

22. The apparatus of claim 21 wherein said delay line is part of a phase locked loop or a delay locked loop.

23. The apparatus of claim 21 wherein said delay line includes an inverter string having a number of inverters and a circuit to tune the delay.

24. The apparatus of claim 23 said circuit to change the number of inverters.

25. The apparatus of claim 21 including a comparator coupled to said capacitor summing network.