SPLIT BLOCK DECODER FOR A NONVOLATILE MEMORY DEVICE

• US 20150117103A1
• Filed: 01/06/2015
• Published: 04/30/2015
• Est. Priority Date: 10/16/2012
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: RHIE, Hyoung Seub
• Granted Patent: US 9,384,838 B2
• Time in Patent Office: Days
• US Class Current: 365/185.11
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address. Row decoding circuitry associated with each group of memory blocks can have a row pitch spacing that is greater than a row pitch spacing of a single memory block and less than or equal to a total row pitch spacing corresponding to the group of memory blocks.

Claims

1. A method for operating a non-volatile memory device having a memory array, wherein the memory array includes a plurality of memory blocks organized as groups of memory blocks, the method comprising:

selecting, by row decoding circuitry, a group of the plurality of memory blocks in response to a first row address;

selecting, by the row decoding circuitry, a memory block of the group for receiving row signals in response to a second row address; and

providing, by first decoder logic of the row decoding circuitry, a super block signal corresponding to each group of the plurality of memory blocks in response to the first row address.

2. The method of claim 1, wherein the row signals includes string select signals corresponding to each memory block of the group, the method further comprising coupling, by discharge devices of the non-volatile memory device, each of the string select signals to ground in response to the group being unselected.

3. The method of claim 2, further comprising controlling each of the discharge devices by logic states of the super block signal.

4. The method of claim 2, wherein the row signals includes ground select signals corresponding to each memory block of the group, the method further comprising coupling, by ground select discharge devices of the non-volatile memory device, each of the ground select signals to ground in response to the group being unselected.

5. The method of claim 4, further comprising controlling each of the ground select discharge devices by logic states of the super block signal.

6. The method of claim 2, further comprising selecting, by a select logic unit of the row decoding circuitry, the group addressed by the first row address and the memory block of the group addressed by the second row address.

7. The method of claim 6, wherein the first row address includes higher order bits of a memory block address.

8. The method of claim 7, further comprising providing, by second decoder logic of the row decoding circuitry, block signals corresponding to each memory block of the group in response to the second row address.

9. The method of claim 8, wherein the block signals include block select signals corresponding to each memory block of the group, and row signals for accessing memory cells of each memory block of the group.

10. The method of claim 8, wherein the block signals include dedicated sets of row signals corresponding to each memory block of the group.

11. A system comprising a plurality of non-volatile memory devices, each of the memory devices comprising:

a memory array including a plurality of memory blocks organized as groups of memory blocks; and

row decoding circuitry configured to select a group of the plurality of memory blocks in response to a first row address and to select a memory block of the group for receiving row signals in response to a second row address;

wherein the row decoding circuitry includes first decoder logic configured to provide a super block signal corresponding to each group of the plurality of memory blocks in response to the first row address.

12. The system of claim 11, further including high voltage level shifters for voltage level shifting the super block signals.

13. The system of claim 11, wherein the row signals includes string select signals corresponding to each memory block of the group, the non-volatile memory device further including discharge devices for coupling each of the string select signals to ground when the group is unselected.

14. The system of claim 13, wherein each of the discharge devices is controlled by logic states of the super block signal.

15. The system of claim 13, wherein the row signals includes ground select signals corresponding to each memory block of the group, the non-volatile memory device further including ground select discharge devices for coupling each of the ground select signals to ground when the group is unselected.

16. The system of claim 13, wherein the row decoding circuitry includes a select logic unit configured to select the group addressed by the first row address and the memory block of the group addressed by the second row address.

17. The system of claim 16, wherein the select logic unit is formed within a row pitch of the group.

18. The system of claim 16, wherein the first decoder logic and the select logic unit are formed on one side of the memory array.

19. The system of claim 16, wherein the first row address includes higher order bits of a memory block address, and wherein the row decoding circuitry includes second decoder logic configured to provide block signals corresponding to each memory block of the group in response to the second row address.

20. The system of claim 19, wherein the first decoder logic includes a first portion formed on one side of the memory array and a second portion formed on an opposite side of the memory array.