BURIED FIELD RING FIELD EFFECT TRANSISTOR (BUF-FET) INTEGRATED WITH CELLS IMPLANTED WITH HOLE SUPPLY PATH

• US 20150118810A1
• Filed: 10/24/2013
• Published: 04/30/2015
• Est. Priority Date: 10/24/2013
• Status: Abandoned Application

• Current Assignee: Anup Bhalla, Hamza Yilmaz, Lingpeng Guan, Madhur Bobde
• Original Assignee: Anup Bhalla, Hamza Yilmaz, Lingpeng Guan, Madhur Bobde
• Inventors: Bobde, Madhur, Bhalla, Anup, Yilmaz, Hamza, Guan, Lingpeng
• Application Number:
  US14/062,319
• Publication Number:
  US 20150118810A1
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/22 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/26553 Through-implantation
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0804 Emitter regions of bipolar transistors
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42304 Base electrodes for bipolar transistors
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66712 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66727 : with a step of recessing the source electrode
• CPC Class Codes: H01L 29/732 : Vertical transistors
• CPC Class Codes: H01L 29/7396 : with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]

Abstract

This invention discloses a semiconductor power device formed in a semiconductor substrate comprises a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region. The semiconductor power device further comprises a body region, a source region and a gate disposed near the top surface of the semiconductor substrate and a drain disposed at a bottom surface of the semiconductor substrate. Source trenches are opened into the highly doped region filled with a conductive trench filling material in electrical contact with the source region near the top surface. A buried field ring regions is disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. In an alternate embodiment, there are doped regions doped with a dopant of a same conductivity type of the buried field ring regions surrounding the sidewalls of the source trenches to function as a charge supply path.

Claims

1. A method for manufacturing a semiconductor power device in a semiconductor substrate comprising:

doping the semiconductor substrate to form a lightly doped lower layer and a highly doped upper layer near a top surface on top of the lightly doped lower layer;

opening a plurality of source connecting trenches into the highly doped upper layer;

implanting buried field ring regions below the source connecting trenches with a dopant of opposite conductivity from the highly doped upper layer;

padding the source connecting trenches with a trench insulation layer and filling the source connecting trenches with a conductive trench filling material; and

forming a body region, a source region and a gate near the top surface of the semiconductor substrate and forming a source electrode metal layer connecting to the source region and the conducting trench filling material in the source connecting trenches.

2. The method of claim 1 wherein:

the step of forming the highly doped upper layer and the lightly doped lower layer comprising a step of forming the highly doped upper layer and the lightly doped lower layer as N type doped layers and implanting the buried field ring regions as P type buried field ring regions.

3. The semiconductor power device of claim 1 further comprising:

forming the semiconductor power device on the semiconductor substrate with a heavily doped N bottom layer to function as the drain of the semiconductor substrate.

4. The semiconductor power device of claim 2 wherein:

the step of forming the highly doped upper layer and the lightly doped lower layer as N type doped layers further comprises a step of forming the highly doped upper layer having a dopant concentration ranging approximately between 1e15 cm−

3 to 5e16 cm−

3 and the lower lightly doped lower layer having a dopant concentration ranging approximately between 1e14 cm−

3 to 5e15 cm−

3.

5. The method of claim 3 wherein:

the step of forming the semiconductor power device on the semiconductor substrate with a heavily doped N bottom layer further comprises a step of forming the semiconductor power device on the heavily doped N bottom layer having a dopant concentration ranging approximately between 1e19 cm−

3 to 1e21 cm−

3.

6. The method of claim 1 wherein:

the step of forming the highly doped upper layer and the lightly doped lower layer further comprises a step of doping the highly doped upper layer and the lightly doped lower layer respectively with an arsenic dopant and a phosphorous dopant.

7. The method of claim 1 wherein:

the step of padding the source connecting trenches with a trench insulation layer further comprises a step of padding the source connecting trenching with an oxide layer and filling the source connecting trenches with a polysilicon as the conductive trench filling material.

8. The method of claim 1 wherein:

the step of opening the source connecting trenches further comprises a step of opening the source connecting trenches into a depth approximately 6 micrometers into the highly doped upper layer and padding the source connecting trenches with an oxide layer having a thickness of approximately 5500 Angstroms.

9. The method of claim 1 wherein:

the step of implanting the buried field ring regions below the source trenches further comprises a step of implanting a P-type dopant to form the buried field ring regions having a dopant concentration ranging approximately between 1e14 cm−

3 to 1e16 cm−

3.

10. The method of claim 1 wherein:

The step of implanting the buried field ring regions below the source trenches further comprises a step of carrying out a tilt angle implant to form charge supply path regions surrounding sidewalls of the source trenches with a dopant of the same conductivity type as the buried field regions