APPARATUSES AND METHODS FOR IDENTIFYING AN EXTREMUM VALUE STORED IN AN ARRAY OF MEMORY CELLS

• US 20150120987A1
• Filed: 10/31/2013
• Published: 04/30/2015
• Est. Priority Date: 10/31/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wheeler, Kyle B.
• Granted Patent: US 9,449,675 B2
• Time in Patent Office: Days
• US Class Current: 711/102
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

The present disclosure includes apparatuses and methods related to identifying an extremum value using sensing circuitry. An example method can include determining a location of an extremum value of a set of N data values stored as vectors in a memory array. A number of operations to determine the location of the extremum value can remain constant with respect to a value of N.

The method can include determining the value of the extremum by reading memory cells coupled to the sense line based on the determined location of the extremum value.

Claims

1. A method for identifying an extremum value, comprising:

determining a location of an extremum value of a set of N stored as vectors in a memory array, wherein a number of operations to determine the location of the extremum value remains constant with respect to a value of N.

2. The method of claim 1, wherein the number of operations to determine the extremum value changes with respect to a length of the vectors.

3. The method of claim 1, wherein the vectors in the memory array are bit vectors, wherein each bit vector represents a respective numerical value.

4. The method of claim 1, comprising identifying the extremum value by reading a sense line based on the determined location of the extremum value.

5. The method of claim 1, wherein each data value of the set of N data values is stored in a respective plurality of memory cells coupled to a respective sense line of a set of N sense lines.

6. The method of claim 1, wherein the extremum value comprises a maximum value.

7. The method of claim 1, wherein the extremum value comprises a minimum value.

8. An apparatus, comprising:

an array of memory cells;

sensing circuitry coupled to the array and configured to;

sense a first number of memory cells coupled to a first access line to determine if one or more of the first number of memory cells stores a target data value, wherein the first access line corresponds to a highest index of a number of bit vectors stored in the array;

sense a second number of memory cells coupled to a second access line corresponding to a lower index of the number of bit vectors;

responsive to a determination that the target data value is stored in one or more memory cells of the first number of memory cells, compare the data stored in the first number of memory cells to the data stored in the second number of memory cells; and

responsive to a result of the comparison indicating one or more memory cell of the first number of memory cells stores the target data value and is coupled to a same sense line as a memory cell of the second number of memory cells that also stores the target data value, storing the result of the comparison in the array of memory cells.

9. A method for identifying an extremum in a set of data stored as vectors in an array of memory cells, the method comprising:

sensing, with sensing circuitry coupled to the array of memory cells, data stored in a group of the memory cells coupled to a particular access line;

performing an operation with the sensing circuitry to determine if the sensed data includes a target data value; and

if the sensed data includes the target data value, determining a location of a sense line that is coupled to a memory cell in the group of memory cells that stores the target data value.

10. The method of claim 9, wherein determining a location of a sense line that is coupled to a memory cell in the group of memory cells that stores the target data value comprises storing the sensed data in a group of the memory cells coupled to a destination access line.

11. The method of claim 10, wherein determining a location of a sense line that is coupled to a memory cell in the group of memory cells that stores the target data value further comprises:

comparing the data stored in the group of memory cells coupled to the destination access line to data stored in a group of the memory cells coupled to another access line to provide output data, wherein the other access line corresponds to a lower index of the vectors than the particular access line.

12. The method of claim 11, wherein determining a location of a sense line that is coupled to a memory cell in the group of memory cells that stores the target data value further comprises:

performing an operation with the sensing circuitry to determine if the output data includes the target data value; and

if the output data includes the target data value, determining a location of a sense line that is coupled to a memory cell in the group of memory cells coupled to the other access line that stores the target data value.

13. The method of claim 12, wherein determining a location of a sense line that is coupled to a memory cell in the group of memory cells coupled to the particular access line that stores the target data value further comprises:

comparing the data stored in the group of memory cells coupled to the destination access line to data stored in a group of the memory cells coupled to a next-most significant access line to provide additional output data, wherein the next-most significant access line corresponds to a lower index of the vectors than the other access line;

performing an operation with the sensing circuitry to determine if the additional output data includes the target data value; and

if the additional output data includes the target data value, determining a location of a sense line that is coupled to a memory cell in the group of memory cells coupled to the next-most significant access line that stores the target data value.

14. The method of claim 13, further comprising repeating the comparison and the determination whether the additional output data includes the target data value for each access line corresponding to a lower index of the vectors than the next-most significant access line and, if the respective output data includes the target data value, determining a location of a sense line that is coupled to a memory cell in the group of memory cells coupled to the respective access line that stores the target data value.

15. The method of claim 10, further comprising storing a bit mask in the group of memory cells coupled to the destination access line prior to sensing the data stored in the group of memory cells coupled to the particular access line.

16. The method of claim 15, wherein the bit mask comprises the data stored in the group of memory cells coupled to the particular access line.

17. The method of claim 11, further comprising inverting data values stored in a number of accumulators associated with the group of memory cells prior to sensing the data stored in the group of memory cells coupled to the particular access line.

18. The method of claim 17, further comprising clearing out data values previously stored in the number of accumulators by storing default data values prior to inverting the default data values stored in the number of accumulators.

19. The method of claim 17, further comprising a second inversion of the data values stored in the number of accumulators that correspond to data stored in the group of memory cells coupled to the particular access line values stored in the number of accumulators after sensing the data stored in the group of memory cells coupled to the particular access line and before performing the operation with the sensing circuitry to determine if the sensed data includes the target data value.

20. The method of claim 19, further comprising inverting the data stored in the other access line corresponding to a next-lower index of the vector prior to comparing the data stored in the group of memory cells coupled to the destination access line to the data stored in the group of memory cells coupled to the other access line to provide the output data.

21. The method of claim 9, wherein performing an operation with the sensing circuitry to determine if the sensed data includes a target data value comprises performing a BlockOR operation with the sensing circuitry.

22. The method of claim 21, wherein performing a BlockOr operation with an accumulator of the sensing circuitry comprises:

charging an I/O line to a level corresponding to the target data value;

transferring the sensed data from a plurality of sense amplifiers to the I/O line; and

determining whether the level of the I/O line changes responsive to transferring the sensed data.

23. The method of claim 22, wherein determining whether the level of the I/O line changes responsive to transferring the sensed data comprises detecting, with a secondary sense amplifier, whether the level changes by at least a threshold amount, wherein the level of the I/O line changing by more than the threshold amount indicates that the sensed data stores the target data value.

24. The method of claim 9, wherein the extremum comprises a maximum and the target data value comprises a binary 1.

25. The method of claim 9, wherein the extremum comprises a minimum and the target data value comprises a binary 0.

26. The method of claim 9, wherein the extremum comprises a plurality of extremums and wherein determining a location of a sense line that is coupled to a memory cell in the group of memory cells that stores the target data value comprises determining locations of a plurality of sense lines that are coupled to memory cells in the group of memory cells that store the target data value.

27. The method of claim 9, wherein the group of memory cells comprises a row of the array of memory cells, wherein each of the vectors is stored in a respective column of the array of memory cells, and wherein each memory cell in the row is coupled to a respective sense line of a plurality of sense lines.

28. The method of claim 9, further comprising, if the sensed data does not includes the target data value:

sensing, with the sensing circuitry coupled to the array of memory cells, data stored in a group of the memory cells coupled to another access line, wherein the other access line corresponds to a lower index of the vectors than the particular access line;

performing an operation with the sensing circuitry to determine if the data sensed from the group of memory cells coupled to the other access line includes the target data value; and

if the data sensed from the group of memory cells coupled to the other access line includes the target data value, determining a location of a sense line that is coupled to a memory cell in the group of memory cells coupled to the other access line that stores the target data value.

29. The method of claim 9, further comprising reading data stored in memory cells coupled to the sense line to determine a value of the extremum.

30. The method of claim 9, wherein sensing, with sensing circuitry coupled to the array of memory cells, data stored in a group of the memory cells coupled to a particular access line comprises reading a row of memory cells of the array of memory cells.

31. An apparatus, comprising:

an array of memory cells storing numerical values as bit-vectors along sense lines; and

control circuitry coupled to the array and configured to control;

sensing, with sensing circuitry coupled to the array of memory cells, data stored in a group of the memory cells coupled to a particular access line;

performing an operation with the sensing circuitry to determine if the sensed data includes a target data value; and

responsive to the sensed data including the target data value, a determining a location of a sense line that is coupled to a memory cell in the group of memory cells that stores the target data value.

32. The apparatus of claim 31, wherein the control circuitry is further configured to control:

storing the sensed data in a group of the memory cells coupled to a destination access line; and

comparing the data stored in the group of memory cells coupled to the destination access line to data stored in a group of the memory cells coupled to another access line to provide output data, wherein the other access line corresponds to a lower index of the bit-vectors than the particular access line.

33. The apparatus of claim 32, wherein the control circuitry is further configured to control:

performing an operation with the sensing circuitry to determine if the output data includes the target data value; and

if the output data includes the target data value, determining a location of a sense line that is coupled to a memory cell in the group of memory cells coupled to the other access line that stores the target data value.

34. The apparatus of claim 33, wherein the control circuitry is further configured to control determining a location of a sense line that is coupled to a memory cell in the group of memory cells coupled to the particular access line that stores the target data value by:

comparing the data stored in the group of memory cells coupled to the destination access line to data stored in a group of the memory cells coupled to a next-most significant access line to provide additional output data, wherein the next-most significant access line corresponds to a lower index of the vectors than the other access line;

performing an operation with the sensing circuitry to determine if the additional output data includes the target data value; and

if the additional output data includes the target data value, determining a location of a sense line that is coupled to a memory cell in the group of memory cells coupled to the next-most significant access line that stores the target data value.

35. The apparatus of claim 34, wherein the control circuitry is further configured to control:

repeating the comparison and the determination whether the additional output data includes the target data value for each access line corresponding to a lower index of the vectors than the next-most significant access line; and

if the respective output data includes the target data value, determining a location of a sense line that is coupled to a memory cell in the group of memory cells coupled to the respective access line that stores the target data value.

36. The apparatus of claim 32, wherein the control circuitry is further configured to control storing of a bit mask in the group of memory cells coupled to the destination access line prior to sensing the data stored in the group of memory cells coupled to the particular access line.

37. The apparatus of claim 36, wherein the bit mask comprises the data stored in the group of memory cells coupled to the particular access line.

38. The apparatus of claim 32, wherein the control circuitry is further configured to control inverting data values stored in a number of accumulators associated with the group of memory cells prior to sensing the data stored in the group of memory cells coupled to the particular access line.

39. The apparatus of claim 38, wherein the control circuitry is further configured to control clearing out data values previously stored in the number of accumulators by storing default data values prior to inverting the default data values stored in the number of accumulators.

40. The apparatus of claim 38, wherein the control circuitry is further configured to control performing a second inversion of the data values stored in the number of accumulators that correspond to data stored in the group of memory cells coupled to the particular access line values stored in the number of accumulators after sensing the data stored in the group of memory cells coupled to the particular access line and before performing the operation with the sensing circuitry to determine if the sensed data includes the target data value.

41. The apparatus of claim 40, wherein the control circuitry is further configured to control inverting the data stored in the other access line corresponding to a next-lower index of the vector prior to comparing the data stored in the group of memory cells coupled to the destination access line to the data stored in the group of memory cells coupled to the other access line to provide the output data.

42. The apparatus of claim 31, wherein the control circuitry is further configured to control performing a BlockOR operation with the sensing circuitry to determine if the sensed data includes the target data value.

43. The apparatus of claim 42, wherein the control circuitry is further configured to control performing a BlockOr operation with an accumulator of the sensing circuitry by:

charging an I/O line to a level corresponding to the target data value;

transferring the sensed data from a plurality of accumulators to the I/O line; and

determining whether the level of the I/O line changes responsive to transferring the sensed data.

44. The apparatus of claim 43, wherein the control circuitry is configured to control detecting, with a secondary sense amplifier, whether the level changes by at least a threshold amount, wherein the level of the I/O line changing by less than the threshold amount indicates that the sensed data stores the target data value to determine whether the level of the I/O line changes responsive to transferring the sensed data comprises.

45. The apparatus of claim 31, wherein control circuitry is further configured to control:

determining a plurality of extremums; and

determining locations of a plurality of sense lines that are coupled to memory cells in the group of memory cells that store the target data value and correspond respectively to each of the plurality of extremums.

46. The apparatus of claim 31, wherein the group of memory cells comprises a row of the array of memory cells, wherein each of the vectors is stored in a respective column of the array of memory cells, and wherein each memory cell in the row is coupled to a respective sense line of a plurality of sense lines.

47. The apparatus of claim 31, wherein, if the sensed data does not include the target data value, the control circuitry is further configured to control:

sensing, with the sensing circuitry coupled to the array of memory cells, data stored in a group of the memory cells coupled to another access line, wherein the other access line corresponds to a lower index of the vectors than the particular access line;

performing an operation with the sensing circuitry to determine if the data sensed from the group of memory cells coupled to the other access line includes the target data value; and

if the data sensed from the group of memory cells coupled to the other access line includes the target data value, determining a location of a sense line that is coupled to a memory cell in the group of memory cells coupled to the other access line that stores the target data value.

48. The apparatus of claim 31, wherein the control circuitry is further configured to control reading data stored in memory cells coupled to the sense line to determine a value of the extremum.

49. An apparatus comprising:

an array of memory cells storing numerical values as bit-vectors along sense lines;

control circuitry coupled to the array and configured to cause;

a determination whether a first number of memory cells coupled to a first access line stores a data value;

a comparison of values in each of the first number of memory cells storing most-significant bit data and coupled to the first access line with corresponding values in each of a second number of memory cells storing second-most-significant bit-data and coupled to a second access line using an AND operation;

values obtained from the AND operation to be written to a bit-mask in the array;

a repetition of a number of comparisons using a number of AND operations of a number of memory cells storing next-most-significant data values and coupled to a first corresponding access line with memory cells storing prior-most-significant data values and coupled to a second corresponding access line until there are no memory cells coupled to any of the access lines that store the data value;

a determination of which memory cells coupled to a sense line in the array store an extremum value based on the comparisons; and

an identification of the extremum value of the array by reading the determined memory cells coupled to the corresponding sense line; and

sensing circuitry coupled to the array and configured to;

sense the number of memory cells storing most-significant data values coupled to the first corresponding access line, the number of memory cells storing second-most-significant data values coupled to the second corresponding access line, and a number of memory cells storing data values of subsequently decreasing significance and coupled to additional corresponding access lines.

50. The apparatus of claim 49, wherein the repetition of the number of comparisons comprises a comparison of data values stored in the bit-mask with a third number of memory cells storing third-most-significant data values and coupled to a third access line.

51. The apparatus of claim 49, wherein the determination whether the first number of memory cells includes the data value is performed by:

control circuitry coupled to the memory array and configured to cause a charging of an input/output (IO) line of the memory array to a voltage; and

sensing circuitry coupled to the memory array and comprising;

a number of primary sense amplifiers coupled to respective pairs of complementary sense lines;

a number of accumulators coupled to the number of primary sense amplifiers; and

a secondary sense amplifier coupled to the IO line and configured to sense whether the voltage of the IO line changes in response to activation of selected decode lines of the array to determine whether data stored in the array includes the data value.

52. The apparatus of claim 49, wherein the determination of which memory cell in the array includes the extremum value is identified as a location of a memory cell in the array that maintains a value in the bit-mask after other values stored in the bit mask have been dropped.

53. An apparatus comprising:

an array of memory cells storing N number of bit-vectors corresponding to numerical values along sense lines;

sensing circuitry coupled to the array and configured to;

sense a first number of memory cells coupled to an access line storing most-significant bit data to determine if there is a data value associated with an extremum value in memory cells of the first number of memory cells;

sense a second number of memory cells coupled to a second access line storing second-most-significant bit data;

compare data values stored in the first number of memory cells to data values stored in the corresponding second number of memory cells;

control circuitry coupled to the array and configured to control;

repeating the sensing and comparing of memory cells coupled to previous-most significant access lines and memory cells coupled to next-most significant access lines until a particular access line coupled to memory cells storing least-significant bit data corresponding to the bit-vectors has been sensed;

determining which sense lines are coupled to memory cells storing an extremum value based on a bit-mask stored in cells coupled to the destination access line; and

identifying extremum values by reading memory cells coupled to a sense line based on the bit-mask stored in the cells coupled to the destination access line.

54. The apparatus of claim 53, wherein the extremum values include one of maximum values and minimum values.

55. The apparatus of claim 53, wherein a number of repetitions to reach the particular access line coupled to memory cells storing the least-significant bit data is associated with a bit-length of the bit-vectors.

56. An apparatus comprising:

an array of memory cells storing N number of bit-vectors;

control circuitry coupled to the array and configured to control;

sensing a first number of memory cells coupled to an access line storing most-significant bit data to determine if there is a data value associated with an extremum value in memory cells of the first number of memory cells, wherein the determining includes;

precharging of a local input/ouput (LIO) line of the array to a precharge voltage; and

selective activation of the first number of memory cells; and

determining whether the precharge voltage of the LIO line changes in response to activation of the selectively activated first number of memory cells;

sensing a second number of memory cells coupled to a second access line storing second-most-significant bit data;

comparing data values stored in the first number of memory cells to data values stored in the corresponding second number of memory cells;

repeating the sensing and the comparing of memory cells coupled to previous-most significant access lines to memory cells coupled to next-most significant access lines until an access line coupled to memory cells storing least-significant bit data has been reached;

determining which sense line is coupled to memory cells storing an extremum value based on a bit-mask stored in a destination row;

identifying an extremum value by reading memory cells coupled to a sense line based on the bit-mask stored in the destination row.

57. The apparatus of claim 56, wherein the destination row indicates a plurality of sense lines coupled to memory cells storing the extremum value.

58. The apparatus of claim 57, wherein identifying an extremum value comprises identifying extremum values by reading memory cells coupled to a plurality of sense lines based on the bit-mask stored in the destination row.