DATA PROCESSING METHOD AND APPARATUS FOR PREFETCHING

• US 20150121014A1
• Filed: 10/24/2013
• Published: 04/30/2015
• Est. Priority Date: 10/24/2013
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: HOLM, Rune, DASIKA, Ganesh Suryanarayan
• Granted Patent: US 9,037,835 B1
• Time in Patent Office: Days
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/6026 Prefetching based on access pattern detection, e.g. stride based prefetch
• CPC Class Codes: G06F 9/3455 using stride
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3832 Value prediction for operands; operand history buffers

Abstract

A data processing device includes processing circuitry 20 for executing a first memory access instruction to a first address of a memory device 40 and a second memory access instruction to a second address of the memory device 40, the first address being different from the second address. The data processing device also includes prefetching circuitry 30 for prefetching data from the memory device 40 based on a stride length 70 and instruction analysis circuitry 50 for determining a difference between the first address and the second address. Stride refining circuitry 60 is also provided to refine the stride length based on factors of the stride length and factors of the difference calculated by the instruction analysis circuitry 50.

Claims

1. A data processing device comprising:

processing circuitry configured to execute a first memory access instruction to a first address of a memory device and a second memory access instruction to a second address of said memory device, wherein said first address is different from said second address;

prefetching circuitry configured to prefetch data from said memory device in dependence on a stride length;

instruction analysis circuitry configured to determine a difference between said first address and said second address;

stride refining circuitry configured to refine said stride length based on factors of said stride length and factors of said difference.

2. A data processing device according to claim 1,

wherein said processing circuitry is configured to execute a first thread comprising said first memory access instruction and a second thread comprising said second memory access instruction.

3. A data processing device according to claim 1,

wherein said first memory access instruction and said second memory access instruction have the same program counter value.

4. A data processing device according to claim 2,

wherein said processing circuitry is configured to execute said first thread and said second thread in either order.

5. A data processing device according to claim 1,

wherein said stride refining circuitry is configured to refine said stride length to a greatest common factor of said stride length and said difference.

6. A data processing device according to claim 1,

wherein said stride refining circuitry is configured to refine said stride length to said difference if said difference is a factor of said stride length.

7. A data processing device according to claim 1, comprising:

stride confidence circuitry, configured to maintain a confidence value of said stride value, to increase said confidence value in response to a memory access instruction directed towards an address of data that has been prefetched by said prefetching unit, and to reset said confidence value in response to said stride refining circuitry refining said stride length.

8. A data processing device according to claim 7,

wherein said prefetching circuitry is configured to prefetch data in further dependence on said confidence value.

9. A data processing device according to claim 7,

wherein said stride confidence circuitry is configured, in response to at least one of:

a ratio of said difference to said stride length being greater than a first predetermined value; and

a ratio of said difference to said stride length being less than a second predetermined value,

to reduce said confidence value.

10. A data processing device according to claim 9,

wherein said first predetermined value is 16.

11. A data processing device according to claim 9,

wherein said second predetermined value is −

16.

12. A data processing device according to claim 9,

wherein at least one of said first predetermined value and said second predetermined value is dependent on a number of threads that said processing circuitry is configured to execute.

13. A data processing device according to claim 1,

wherein said prefetching circuitry is configured to prefetch data between said first address and said second address in addition to data not between said first address and said second address.

14. A method of prefetching data from a memory device, comprising the steps:

executing a first memory access instruction to a first address of a memory device and a second memory access instruction to a second address of said memory device, wherein said first address is different from said second address;

determining a difference between said first address and said second address;

refining a stride length based on factors of said stride length and factors of said difference;

prefetching data from said memory device in dependence on said stride length.

15. A data processing device comprising:

processing means for executing a first memory access instruction to a first address of a memory device and a second memory access instruction to a second address of said memory device, wherein said first address is different from said second address;

prefetching means for prefetching data from said memory device in dependence on a stride length;

instruction analysis means for determining a difference between said first address and said second address;

stride refining means for refining said stride length based on factors of said stride length and factors of said difference.