SYSTEMS AND METHODS FOR SECURE PROCESSING WITH EMBEDDED CRYPTOGRAPHIC UNIT

• US 20150121086A1
• Filed: 10/31/2013
• Published: 04/30/2015
• Est. Priority Date: 10/31/2013
• Status: Active Grant

• Current Assignee: Block, Inc. (f/k/a Square, Inc.)
• Original Assignee: Kili Technology Corporation (Block, Inc. (f/k/a Square, Inc.))
• Inventors: Smith, Malcolm Ronald, Vadera, Kshitiz, Rezayee, Afshin, Zagrodney, Mark Philip, Ng, Kevin Ka Wai
• Granted Patent: US 9,135,472 B2
• Time in Patent Office: Days
• US Class Current: 713/189
• CPC Class Codes: G06F 21/556 involving covert channels, i.e. data leakage between processes inhibiting the analysis of circuitry or operation with measures against power attack G06F21/755
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: H04L 2463/102 applying security measure for e-commerce data processing systems or methods, specially adapted for e-commerce G06Q30/00
• CPC Class Codes: H04L 63/0492 by using a location-limited connection, e.g. near-field communication or limited proximity of entities
• CPC Class Codes: H04L 63/0853 using an additional device, e.g. smartcard, SIM or a different communication terminal cryptographic mechanisms or cryptographic arrangements for entity authentication involving additional secure or trusted devices H04L9/3234
• CPC Class Codes: H04L 9/0894 Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage
• CPC Class Codes: H04L 9/3236 using cryptographic hash functions

Abstract

Processor system with a general purpose processor and a cryptographic processor dedicated to performing cryptographic operations and enforcing the security of critical security parameters. The cryptographic processor prevents exposure of critical security parameters outside the cryptographic processor itself, and instead implements a limited scripting engine, which can be used by the general purpose processor to execute operations that require the critical security parameters.

Claims

1. A non-transitory computer readable medium storing instructions executable by a cryptographic processor, the instructions which when executed by the cryptographic processor, cause the cryptographic processor to carry out a method of cryptographic processing in conjunction with a general purpose processor, the method comprising:

receiving a script identifier from the general purpose processor;

verifying that a script identified by the script identifier is authorized for execution on the cryptographic processor; and

executing the script to produce a script result.

2. The non-transitory computer readable medium of claim 1, wherein the method further comprises determining whether the script result comprises a critical security parameter that cannot be output from the cryptographic processor in unencrypted form.

3. The non-transitory computer readable medium of claim 2, wherein the method further comprises encrypting at least the critical security parameter in the script result using a secret key stored in a protected memory of the cryptographic processor.

4. The non-transitory computer readable medium of claim 3, wherein the protected memory of the cryptographic processor is not readable externally to the cryptographic processor.

5. The non-transitory computer readable medium of claim 1, wherein the method further comprises transmitting the script result to the general purpose processor.

6. The non-transitory computer readable medium of claim 1, wherein the method further comprises:

receiving the script from the general purpose processor; and

retrieving a script verification value from a protected memory of the cryptographic processor, the protected memory not readable by the general purpose processor,

wherein the verifying comprises computing a second script verification value based on the received script, and comparing the second script verification value to the retrieved script verification value.

7. The non-transitory computer readable medium of claim 1, wherein the instructions specify a limited instruction set that limits instructions able to be used in the script.

8. The non-transitory computer readable medium of claim 7, wherein the limited instruction set is non-Turing-equivalent.

9. The non-transitory computer readable medium of claim 7, wherein the limited instruction set excludes conditional branching instructions.

10. The non-transitory computer readable medium of claim 7, wherein the limited instruction set excludes loop instructions.

11. A cryptographic processing unit for cryptographic processing in conjunction with a general purpose processor, the cryptographic processing unit comprising:

a cryptographic processor, the cryptographic processor configured to;

receive a script identifier from the general purpose processor;

verify that a script identified by the script identifier is authorized for execution on the cryptographic processor; and

execute the script to produce a script result.

12. The cryptographic processing unit of claim 11, wherein the cryptographic processor is further configured to determine whether the script result comprises a critical security parameter that cannot be output from the cryptographic processor in unencrypted form.

13. The cryptographic processing unit of claim 12, further comprising a protected memory that stores a secret key, and wherein the cryptographic processor is further configured to encrypt at least the critical security parameter in the script result using the secret key.

14. The cryptographic processing unit of claim 13, wherein the protected memory is not readable externally to the cryptographic processor.

15. The cryptographic processing unit of claim 11, wherein the cryptographic processor is further configured to transmit the script result to the general purpose processor.

16. The cryptographic processing unit of claim 11, further comprising a protected memory not readable by the general purpose processor, wherein the cryptographic processor is further configured to:

receive the script from the general purpose processor; and

retrieve a script verification value from the protected memory,

wherein the verifying comprises computing a second script verification value based on the received script, and comparing the second script verification value to the retrieved script verification value.

17. The cryptographic processing unit of claim 11, further comprising a non-transitory computer readable memory, wherein the cryptographic processor is configured by instructions stored in the non-transitory computer readable memory, and wherein the instructions specify a limited instruction set that limits instructions able to be used in the script.

18. The cryptographic processing unit of claim 17, wherein the limited instruction set is non-Turing-equivalent.

19. The cryptographic processing unit of claim 17, wherein the limited instruction set excludes conditional branching instructions.

20. The cryptographic processing unit of claim 17, wherein the limited instruction set excludes loop instructions.

21. The cryptographic processing unit of claim 13, wherein the general purpose processor executes a set of instructions stored in a general non-transitory computer readable memory, and wherein the cryptographic processing unit is configured to:

access the general non-transitory computer readable memory to read the set of instructions; and

verify, using at least one verification value stored in the protected memory, that the set of instructions has not been altered.

22. The cryptographic processing unit of claim 21, wherein the general non-transitory computer readable memory is accessible via a general debugging interface, and wherein the cryptographic processing unit further comprises a cryptographic processing unit debugging interface, wherein each of the general debugging interface and the cryptographic processing unit debugging interface is independently controlled.

23. The cryptographic processing unit of claim 22, wherein the general debugging interface is controlled using a first electronic fuse block, and wherein the cryptographic processing unit comprises a second electronic fuse block for controlling the cryptographic processing unit debugging interface.

24. The cryptographic processing unit of claim 23, wherein the cryptographic processor is configured to control the first and second electronic fuse blocks.

25. The cryptographic processing unit of claim 22, wherein the general debugging interface and the cryptographic processing unit debugging interface are JTAG interfaces.

26. The cryptographic processing unit of claim 11, further comprising a clock source for both the general purpose processor and the cryptographic processor, wherein the clock source is manipulable by the cryptographic processor but not the general purpose processor.

27. The cryptographic processing unit of claim 11, further comprising a power supply for providing power to the general purpose processor and the cryptographic processor, wherein the power supply is controllable by the cryptographic processor but not the general purpose processor.

28. A cryptographic processor system comprising:

a general purpose unit comprising;

a general purpose processor configured to execute a general instruction set;

a cryptographic unit comprising;

a protected memory not readable by the general purpose processor; and

a cryptographic processor configured to;

receive a script identifier from the general purpose processor;

verify that a script identified by the script identifier is authorized for execution on the cryptographic processor; and

execute the script to produce a script result.

29. The processor system of claim 28, further comprising a communications interface between the general purpose processor and the cryptographic processor.

30. The processor system of claim 29, wherein the communications interface is a universal asynchronous receiver transmitter, and wherein the universal asynchronous receiver transmitter communicates with each of the general purpose processor and the cryptographic processor via a peripheral bus.

31. The processor system of claim 28, further comprising a general debugging interface coupled to the general purpose unit and a cryptographic unit debugging interface coupled to the cryptographic processing unit, wherein each of the general debugging interface and the cryptographic unit debugging interface is independently controlled.

32. The processor system of claim 31, wherein the general debugging interface is controlled using a first electronic fuse block, and wherein the cryptographic unit debugging interface is controlled using a second electronic fuse block.

33. The processor system of claim 32, wherein both the first and second electronic fuse blocks are controllable by the cryptographic processor.

34. The processor system of claim 31, wherein the general debugging interface and the cryptographic unit debugging interface are JTAG interfaces.

35. The processor system of claim 28, further comprising a clock source for both the general purpose processor and the cryptographic processor, wherein the clock source is settable by the cryptographic processor but not the general purpose processor.

36. The processor system of claim 28, further comprising a power supply for both the general purpose processor and the cryptographic processor, wherein the power supply is controllable by the cryptographic processor but not the general purpose processor.

37. The processor system of claim 28, wherein the cryptographic processor is further configured to determine whether the script result comprises a critical security parameter that cannot be output from the cryptographic processor in unencrypted form.

38. The processor system of claim 37, wherein the protected memory stores a secret key, and wherein the cryptographic processor is further configured to encrypt at least the critical security parameter in the script result using the secret key.

39. The processor system of claim 38, wherein the protected memory is not readable externally to the cryptographic processing unit.

40. The processor system of claim 29, wherein the cryptographic processor is further configured to transmit the script result to the general purpose processor.

41. The processor system of claim 29, wherein the cryptographic processor is further configured to:

receive the script from the general purpose processor; and

retrieve a script verification value from the protected memory,

wherein the verifying comprises computing a second script verification value based on the received script, and comparing the second script verification value to the retrieved script verification value.

42. The processor system of claim 29, wherein the cryptographic processing unit further comprises a non-transitory computer readable memory, wherein the cryptographic processor is configured by instructions stored in the non-transitory computer readable memory, and wherein the instructions specify a limited instruction set that limits instructions able to be used in the script.

43. The processor system of claim 42, wherein the limited instruction set is non-Turing-equivalent.

44. The processor system of claim 42, wherein the limited instruction set excludes conditional branching instructions.

45. The processor system of claim 42, wherein the limited instruction set excludes loop instructions.

46. The processor system of claim 29, wherein the cryptographic processor is configured to halt the general purpose processor if a fault is detected.

47. The processor system of claim 29, wherein the cryptographic unit is configured to flush state if a fault is detected, and to disable at least one external interface of the processor system.

48. The processor system of claim 29, further comprising a memory access block, wherein the general purpose unit further comprises a general purpose unit computer-readable memory storing a set of instructions executable by the general purpose processor, and wherein the cryptographic processor is configured to:

access the general purpose unit computer readable memory via the memory access block to read the set of instructions;

verify, using at least one verification value stored in the protected memory, that the set of instructions has not been altered.

49. The processor system of claim 29, wherein the general purpose unit comprises a general volatile memory, and wherein the cryptographic unit comprises a protected volatile memory that is accessible only to the cryptographic processor.

50. The processor system of claim 49, wherein the cryptographic processor is configured to write a data item to the protected volatile memory.

51. The processor system of claim 50, wherein the cryptographic unit is configured to read the data item from the protected volatile memory upon subsequently receiving a script for execution.

52. The processor system of claim 50, wherein the cryptographic unit is certified for compliance with a computer security standard, and wherein the general purpose unit is excluded from certification.

53. The processor system of claim 52, wherein the computer security standard is FIPS 140-2.

54. The processor system of claim 53, wherein the computer security standard is FIPS 140-2 Level 3.

55. The processor system of claim 50, wherein the general purpose unit, the cryptographic unit and the communications interface are provided on a single die.

56. The processor system of claim 50, wherein the general purpose unit is provided on a first die and the cryptographic unit is provided on a second die.