MULTI-PROTOCOL I/O INTERCONNECT TIME SYNCHRONIZATION

• US 20150121115A1
• Filed: 12/30/2014
• Published: 04/30/2015
• Est. Priority Date: 12/27/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chandra, Prashant R., Yudovich, Vladimir, Galil, Eran, Kugman, Efraim
• Granted Patent: US 9,164,535 B2
• Time in Patent Office: Days
• US Class Current: 713/400
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: H04J 3/0667 Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays arrangements for monitoring round trip delays in packet switching networks H04L43/0864
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node
• CPC Class Codes: H04L 7/00 Arrangements for synchronising receiver with transmitter synchronisation of generators of electric oscillations or pulses H03L7/00

Abstract

Described are embodiments of methods, apparatuses, and systems for time synchronization of a multi-protocol I/O interconnect of computer apparatus. A method for synchronizing time across the multi-protocol I/O interconnect may include providing a first local time of a first switch of a switching fabric of a multi-protocol interconnect to a second switch of the switching fabric, and adjusting a second local time of the second switch to the first local time. Other embodiments may be described and claimed.

Claims

1. An integrated circuit device comprising:

a switch,

a local clock wherein the local clock is a free-running oscillator, and

at least one port,

wherein the integrated circuit device is a first integrated circuit device and is to;

send a first time synchronization message to a second integrated circuit device at a first local time of the first integrated circuit device;

receive by a first port of the at least one port a second time synchronization message from the second integrated circuit device wherein the second time synchronization message comprises an ordered data set comprising a time stamp point,

generate a time stamp when the time stamp point of the second time synchronization message passes a reference point in the first integrated circuit device wherein the time stamp is at a second local time of the first integrated circuit device,

receive a third time synchronization message comprising a third and a fourth local time of the second integrated circuit device wherein the third time synchronization message is received at a different time than the second time synchronization message,

determine a first offset value of local time of the first integrated circuit device from local time of the second integrated circuit device wherein determining includes calculating the first offset value based at least in part on the time stamp generated in the first integrated circuit device and the first local time of the first integrated circuit device, and the third and fourth local times of the second integrated circuit device and on time asymmetry corrections between transmit and receive paths between the first integrated circuit device and the second integrated circuit device, wherein the time asymmetry corrections correct for asymmetry between the transmit and receive paths between the first integrated circuit device and the second integrated circuit device.

2. The integrated circuit device of claim 1 wherein the time stamp has a resolution of at least 8 nanoseconds.

3. The integrated circuit device of claim 1 wherein the integrated circuit device is also to determine a frequency offset value wherein the frequency offset value reflects the offset in frequency between a clock of the second integrated circuit device and the free-running oscillator of the first integrated circuit device.

4. The integrated circuit device of claim 1 wherein the integrated circuit device is also to be part of a multiprotocol input/output fabric that is to transmit data between devices according to PCI express, USB, and DisplayPort protocols.

5. The integrated circuit device of claim 1 wherein the first time synchronization message is a time sync notification ordered set (TSNOS).

6. The integrated circuit device of claim 1 wherein the integrated circuit device also includes a time-offset register to store a determined time offset value.

7. The integrated circuit device of claim 3 wherein the integrated circuit device also includes a frequency-offset register to store a determined frequency-offset value.

8. The integrated circuit device of claim 1 wherein the integrated circuit device is also to send by a second port of the at least one port the offset value of local time of the first integrated circuit device from local time of the second integrated circuit device to a third integrated circuit device.

9. The integrated circuit device of claim 1 wherein the integrated circuit device is also to determine a second offset value of a local time of the first integrated circuit device from a local time of a third integrated circuit device wherein the second offset value is a sum of a third offset value of a local time of the second integrated circuit device from a local time of the third integrated circuit device and the first offset value of a local time of the first integrated circuit device from a local time of the second integrated circuit device and wherein the third time synchronization message additionally comprises the third offset value.

10. A system comprising:

a processor,

memory operably coupled to the processor, and

an input output (I/O) interconnect operably coupled to the processor, wherein the input output interconnect comprises;

an integrated circuit device comprising;

a switch,

a local clock wherein the local clock is a free-running oscillator, and

at least one port,

wherein the integrated circuit device is a first integrated circuit device and is to;

send a first time synchronization message to a second integrated circuit device at a first local time of the first integrated circuit device;

receive by a first port of the at least one port a second time synchronization message from the second integrated circuit device wherein the second time synchronization message comprises an ordered data set comprising a time stamp point,

generate a time stamp when the time stamp point of the second time synchronization message passes a reference point in the first integrated circuit device wherein the time stamp is at a second local time of the first integrated circuit device,

receive a third time synchronization message comprising a third and a fourth local time of the second integrated circuit device wherein the third time synchronization message is received at a different time than the second time synchronization message,

determine an offset value of local time of the first integrated circuit device from local time of the second integrated circuit device wherein determining includes calculating the offset value based at least in part on the time stamp generated in the first integrated circuit device and the first local time of the first integrated circuit device, and the third and fourth local times of the second integrated circuit device and on time asymmetry corrections between transmit and receive paths between the first integrated circuit device and the second integrated circuit device, wherein the time asymmetry corrections correct for asymmetry between the transmit and receive paths between the first integrated circuit device and the second integrated circuit device.

11. The integrated circuit device of claim 10 wherein the time stamp has a resolution of at least 8 nanoseconds.

12. The integrated circuit device of claim 10 wherein the integrated circuit device is also to determine a frequency offset value wherein the frequency offset value reflects the offset in frequency between a clock of the second integrated circuit device and the free-running oscillator of the first integrated circuit device.

13. The integrated circuit device of claim 10 wherein the integrated circuit device is also to be part of a multiprotocol input/output fabric that is to transmit data between devices according to PCI express, USB, and DisplayPort protocols.

14. The integrated circuit device of claim 10 wherein the first time synchronization message is a time sync notification ordered set (TSNOS).

15. The integrated circuit device of claim 10 wherein the integrated circuit device also includes a time-offset register to store a determined time offset value.

16. The integrated circuit device of claim 12 wherein the integrated circuit device also includes a frequency-offset register to store a determined frequency-offset value.

17. The integrated circuit device of claim 10 wherein the integrated circuit device is also to send by a second port of the at least one port the offset value of local time of the first integrated circuit device from local time of the second integrated circuit device to a third integrated circuit device.

18. The integrated circuit device of claim 10 wherein the integrated circuit device is also to determine an additional offset value of a local time of the first integrated circuit device from a local time of a third integrated circuit device wherein the additional offset value is a sum of an offset value of a local time of the second integrated circuit device from a local time of the third integrated circuit device and the offset value of a local time of the first integrated circuit device from a local time of the second integrated circuit device.