PROVIDING BUS RESILIENCY IN A HYBRID MEMORY SYSTEM

• US 20150121139A1
• Filed: 10/30/2013
• Published: 04/30/2015
• Est. Priority Date: 10/29/2013
• Status: Active Grant

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: Lenovo Singapore Pte Limited (Lenovo Group Ltd.)
• Inventors: KOCHAR, SUMEET, ONO, MAKOTO
• Granted Patent: US 9,239,807 B2
• Time in Patent Office: Days
• US Class Current: 714/29
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 13/1668 Details of memory controller

Abstract

In a hybrid memory system that includes a host memory controller and a non-volatile memory DIMM, where the DIMM is coupled to the host memory controller by a memory bus, the DIMM includes non-volatile memory, a DIMM bus adapter, and a local memory controller, the local memory controller is configured to control memory accesses within the DIMM, the DIMM bus adapter is configured to adapt the local memory controller to the bus for memory communications with the host memory controller in accordance with a bus protocol, bus resiliency may be provided by: discovering, by the DIMM bus adapter, a memory error in the DIMM; providing, by the DIMM bus adapter to the host memory controller, an indication of an error by emulating a hardware error native to the bus protocol; and performing, by the host memory controller, one or more resiliency measures responsive to the indication of the error.

Claims

1. A method of providing bus resiliency in a hybrid memory system, the hybrid memory system comprising a host memory controller and a non-volatile memory DIMM (Dual Inline Memory Module), the DIMM coupled to the host memory controller by a memory bus, the DIMM comprising non-volatile memory, a DIMM bus adapter, and a local memory controller, the local memory controller configured to control memory accesses within the DIMM, the DIMM bus adapter configured to adapt the local memory controller to the bus for memory communications with the host memory controller in accordance with a bus protocol, the method comprising:

discovering, by the DIMM bus adapter, a memory error in the DIMM;

providing, by the DIMM bus adapter to the host memory controller, an indication of an error by emulating a hardware error native to the bus protocol; and

performing, by the host memory controller, one or more resiliency measures responsive to the indication of the error.

2. The method of claim 1, further comprising:

discovering, by a driver for the DIMM, the emulated hardware error; and

managing, by the driver, the DIMM responsive to the error.

3. The method of claim 1, wherein resiliency measures include sparing a portion of the non-volatile memory of the DIMM in memory of a different DIMM.

4. The method of claim 1, further comprising mirroring memory of the DIMM in memory of a different DIMM and the resiliency measures include failing over to the memory of the different DIMM.

5. The method of claim 1, wherein the memory bus comprises a Peripheral Component Interconnect Express (PCIe) bus and the bus protocol comprises a PCIe bus protocol.

6. The method of claim 1, wherein the memory bus comprises a Double Data Rate (DDR) bus and the bus protocol comprises a DDR bus protocol.

7. A method of providing bus resiliency in a hybrid memory system, the hybrid memory system comprising a host memory controller and a non-volatile memory DIMM (Dual Inline Memory Module), the DIMM coupled to the host memory controller by a memory bus, the DIMM comprising non-volatile memory, a DIMM bus adapter, and a local memory controller, the local memory controller configured to control memory accesses within the DIMM, the DIMM bus adapter configured to adapt the local memory controller to the bus for memory communications with the host memory controller in accordance with a bus protocol, the method comprising:

discovering, by the DIMM bus adapter, a memory error in the DIMM;

providing, by the DIMM bus adapter to the host memory controller, an indication of an error in a form not native to the bus protocol;

discovering, by a driver, the indication of the error; and

performing, by the driver, one or more resiliency measures responsive to the indication of the error.

8. The method of claim 7, wherein resiliency measures include sparing a portion of the non-volatile memory of the DIMM in memory of a different DIMM.

9. The method of claim 7, further comprising mirroring memory of the DIMM in memory of a different DIMM and the resiliency measures include failing over to the memory of the different DIMM.

10. The method of claim 7, wherein the memory bus comprises a Peripheral Component Interconnect Express (PCIe) bus and the bus protocol comprises a PCIe bus protocol.

11. The method of claim 7, wherein the memory bus comprises a Double Data Rate (DDR) bus and the bus protocol comprises a DDR bus protocol.

12-20. -20. (canceled)