ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME

• US 20150123118A1
• Filed: 10/01/2014
• Published: 05/07/2015
• Est. Priority Date: 11/07/2013
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: YEOM, Jung-Min, KIM, Jeong-Yeon
• Granted Patent: US 9,337,346 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An array substrate for an electronic display includes a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; an oxide semiconductor layer on the gate insulating layer; a source electrode and a drain electrode on the oxide semiconductor layer; a silicide layer on the source and drain electrodes; and a first passivation layer on the source electrode and the drain electrode. The array substrate and fabrication method thereof prevent degradation of a thin-film transistor (TFT) used in driving pixels of the electronic display.

Claims

1. An array substrate comprising:

a substrate;

a gate electrode on the substrate;

a gate insulating layer on the gate electrode;

an oxide semiconductor layer on the gate insulating layer;

a source electrode and a drain electrode on the oxide semiconductor layer;

a silicide layer on the source electrode and the drain electrode; and

a first passivation layer on the source electrode and the drain electrode.

2. The array substrate of claim 1, wherein the source electrode and the drain electrode each have a double-layered structure that includes a first layer of one of Mo, Ti, and MoTi, and a second layer of Cu on the first layer.

3. The array substrate of claim 1, further comprising a pixel electrode connected to the drain electrode.

4. The array substrate of claim 3, further comprising:

a second passivation layer on the first passivation layer;

a common electrode on the second passivation layer; and

a third passivation layer on the common electrode,

wherein the first to third passivation layers includes respective drain contact holes exposing the drain electrode, and

wherein the pixel electrode is on the third passivation layer and includes a plurality of bar-shaped openings.

5. A method of an array substrate, comprising:

forming a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode and a drain electrode, on a substrate;

injecting a gas mixture containing silane (SiH₄) onto the source electrode and the drain electrode to form a silicide layer on the source electrode and the drain electrode;

performing a surface treatment for a back channel region of the oxide semiconductor layer between the source electrode and the drain electrode having the silicide layer thereon; and

forming a first passivation layer on the source electrode and the drain electrode.

6. The method of claim 5, wherein the gas mixture contains one of nitrogen (N₂), helium (He), and argon (Ar).

7. The method of claim 5, wherein the surface treatment is performed using one of an oxygen (O₂) plasma treatment, an ozone (O₃) treatment, and a thermal treatment in an oxygen atmosphere.

8. The method of claim 7, wherein the oxygen plasma treatment is performed with oxygen injection.

9. The method of claim 7, wherein the ozone treatment is performed with UV irradiation in an ozone atmosphere.

10. The method of claim 7, wherein the thermal treatment in an oxygen atmosphere is performed with heat of about 100 degrees Celsius to about 300 degrees Celsius.

11. The method of claim 5, wherein the first passivation layer is formed using a gas mixture containing silane (SiH₄) and nitrous oxide (N₂O).

12. The method of claim 6, wherein injecting the gas mixture, performing the surface treatment, and forming the first passivation layer are conducted in the same chamber, and the gas mixture is injected onto the source electrode and the drain electrode in a state that the gas mixture is not ionized.

13. The method of claim 5, wherein in forming the gate electrode, the source electrode, and the drain electrode have a double-layered structure that includes a first layer of one of Mo, Ti, and MoTi, and a second layer of Cu on the first layer.

14. The method of claim 5, further comprising forming a pixel electrode connected to the drain electrode after the step d).

15. The method of claim 14, further comprising:

forming a second passivation layer on the first passivation layer;

forming a common electrode on the second passivation layer; and

forming a third passivation layer on the common electrode,

wherein the pixel electrode is on the third passivation layer, includes a plurality of bar-shaped openings, and contacts the drain electrode through respective drain contact holes in the first to third passivation layers.