WAFER LEVEL PACKAGING TECHNIQUES
First Claim
1. A packaged integrated circuit (IC) structure comprising:
- a first substrate comprising a CMOS device and a CMOS bond ring,a second substrate comprising a MEMS device and a MEMS bond ring, the MEMS bond ring surrounding a periphery of the MEMS device and being bonded to the CMOS bond ring, anda protection layer covering outer sidewalls of the MEMS bond ring and outer sidewalls of the CMOS bond ring, and further covering an outer sidewall of the first substrate and does not cover an outer sidewall of the second substrate.
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Accused Products
Abstract
In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.
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Citations
20 Claims
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1. A packaged integrated circuit (IC) structure comprising:
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a first substrate comprising a CMOS device and a CMOS bond ring, a second substrate comprising a MEMS device and a MEMS bond ring, the MEMS bond ring surrounding a periphery of the MEMS device and being bonded to the CMOS bond ring, and a protection layer covering outer sidewalls of the MEMS bond ring and outer sidewalls of the CMOS bond ring, and further covering an outer sidewall of the first substrate and does not cover an outer sidewall of the second substrate. - View Dependent Claims (2, 3, 4, 5)
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6. A wafer level package structure, comprising:
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a first substrate; a second substrate; an array of bond ring structures arranged between the first and second substrates, wherein interior sidewalls of a bond ring structure define a cavity between a first surface of the first substrate and a first surface of the second substrate; and a test line arranged on or proximate to the first surface of the second substrate, wherein the test line is arranged in a scribe line area between opposing outer sidewalls of neighboring bond ring structures and is electrically coupled to a device on the second substrate. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method comprising:
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providing a first wafer including a plurality of CMOS die and having CMOS bond rings associated therewith, wherein CMOS scribe line regions are arranged between neighboring CMOS die, providing a deep trench aligned within a CMOS scribe line region in the first wafer, providing a second wafer including a plurality of MEMS die having MEMS bond rings associated therewith, wherein MEMS scribe line regions are arranged between neighboring MEMS die and correspond to the CMOS scribe line regions, providing a test line structure aligned within a MEMS scribe line region on the second wafer, bonding the first wafer to the second wafer by bonding the CMOS bond rings to the MEMS bond rings, wherein the deep trench is aligned over the test line structure after bonding, and dicing the bonded first and second wafers along the CMOS and MEMS scribe line regions. - View Dependent Claims (17, 18, 19, 20)
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Specification