WAFER LEVEL PACKAGING TECHNIQUES

• US 20150123129A1
• Filed: 11/05/2013
• Published: 05/07/2015
• Est. Priority Date: 11/05/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Teng, Yi-Chuan, Peng, Jung-Huei, Tsai, Shang-Ying, Hung, Li-Min, Huang, Yao-Te, Cho, Chin-Yi
• Granted Patent: US 9,269,679 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81C 99/0045 End test of the packaged device
• CPC Class Codes: B81C 99/005 Test apparatus
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/0605 Shape
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/83194 Lateral distribution of the layer connectors
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/16235 Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip

Abstract

In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.

Claims

1. A packaged integrated circuit (IC) structure comprising:

a first substrate comprising a CMOS device and a CMOS bond ring,

a second substrate comprising a MEMS device and a MEMS bond ring, the MEMS bond ring surrounding a periphery of the MEMS device and being bonded to the CMOS bond ring, and

a protection layer covering outer sidewalls of the MEMS bond ring and outer sidewalls of the CMOS bond ring, and further covering an outer sidewall of the first substrate and does not cover an outer sidewall of the second substrate.

2. The packaged IC structure of claim 1, wherein the outer sidewall of the second substrate meets an outer sidewall of the protection layer to define a planar surface at which the packaged IC structure was diced.

3. The packaged IC structure of claim 1, wherein the outer sidewalls of the MEMS bond ring and CMOS bond ring are laterally recessed relative to the outer sidewall of the first substrate.

4. The packaged IC structure of claim 1, wherein the MEMS bond ring and CMOS bond ring meet to form an enclosed cavity which is in fluid communication with the MEMS device and which is hermetically sealed from an ambient environment surrounding the packaged IC structure.

5. The packaged IC structure of claim 1, further comprising an electrical connection structure connecting the CMOS device to a top side of the first substrate, the top side opposing a bottom side of the first substrate on which the CMOS bond ring is arranged.

6. A wafer level package structure, comprising:

a first substrate;

a second substrate;

an array of bond ring structures arranged between the first and second substrates, wherein interior sidewalls of a bond ring structure define a cavity between a first surface of the first substrate and a first surface of the second substrate; and

a test line arranged on or proximate to the first surface of the second substrate, wherein the test line is arranged in a scribe line area between opposing outer sidewalls of neighboring bond ring structures and is electrically coupled to a device on the second substrate.

7. The wafer level package structure of claim 6, further comprising:

a deep trench in the first substrate, wherein the deep trench is aligned in the scribe line area over the test line.

8. The wafer level package structure of claim 7, wherein the deep trench is filled with a protection material including photo resist, polyimide, epoxy, spin-on-glass material, or molding material.

9. The wafer level package structure of claim 6, wherein the cavity is filled with an inert gas.

10. The wafer level package structure of claim 6, wherein the first substrate comprises a CMOS device and the second substrate comprises a MEMS device.

11. The wafer level package structure of claim 10, wherein a bond ring structure comprises a CMOS bond ring on the first substrate and a MEMS bond ring on the second substrate.

12. The wafer level package structure of claim 11, wherein the MEMS bond ring is comprised of a material selected from a group consisting of indium, gold, tin, copper, aluminum, germanium and combinations thereof.

13. The wafer level package structure of claim 11, wherein the CMOS bond ring is comprised of a material selected from a group consisting of indium, gold, tin, copper, aluminum, germanium and combinations thereof.

14. The wafer level package structure of claim 11, wherein a bond between the MEMS bond ring and CMOS bond ring is a eutectic metal bond or a eutectic Al/Ge bond.

15. The wafer level package structure of claim 6, further comprising:

a through silicon via, a ball grid array, or a re-distribution layer arranged on a top side of the first substrate to provide electrical connection from the top side of the first substrate.

16. A method comprising:

providing a first wafer including a plurality of CMOS die and having CMOS bond rings associated therewith, wherein CMOS scribe line regions are arranged between neighboring CMOS die,

providing a deep trench aligned within a CMOS scribe line region in the first wafer,

providing a second wafer including a plurality of MEMS die having MEMS bond rings associated therewith, wherein MEMS scribe line regions are arranged between neighboring MEMS die and correspond to the CMOS scribe line regions,

providing a test line structure aligned within a MEMS scribe line region on the second wafer,

bonding the first wafer to the second wafer by bonding the CMOS bond rings to the MEMS bond rings, wherein the deep trench is aligned over the test line structure after bonding, and

dicing the bonded first and second wafers along the CMOS and MEMS scribe line regions.

17. The method of claim 16, wherein the deep trench is isolated from an ambient environment after bonding, further comprising:

opening the deep trench of the second wafer after bonding,

probing the test line structure through the opened deep trench and performing an electrical test on a MEMS die using the test line structure.

18. The method of claim 16, further comprising:

after the first and second wafers have been bonded but prior to dicing, filling the deep trench with a protection material to cover the test line structure.

19. The method of claim 16, wherein bonding the first wafer to the second wafer forms cavities which are laterally bounded by MEMS bond rings and corresponding CMOS bond rings and which are vertically bounded by the first wafer and the second wafer.

20. The method of claim 16, further comprising:

forming a through silicon via, ball grid array, or re-distribution layer on a top side of the first wafer to form an electrical connection to a CMOS device on the first wafer.