INCREASED SPACE BETWEEN EPITAXY ON ADJACENT FINS OF FINFET

• US 20150123146A1
• Filed: 11/04/2013
• Published: 05/07/2015
• Est. Priority Date: 11/04/2013
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: FRONHEISER, Jody A., LEE, Bongki, KRISHNAN, Bharat, LIU, Jinping
• Granted Patent: US 9,165,767 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02587 Structure
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxy is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxy on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume.

Claims

1. A method, comprising:

providing a semiconductor structure, the structure comprising a semiconductor substrate and a plurality of semiconductor fins coupled to the semiconductor substrate;

growing epitaxy on a top surface of the plurality of semiconductor fins, wherein epitaxy on adjacent fins is separated by a space; and

modifying the epitaxy to increase the space between adjacent epitaxy while increasing a volume of the epitaxy.

2. The method of claim 1, wherein the modifying comprises modifying the epitaxy to have increased growth in a first direction of the plurality of semiconductor fins with respect to the substrate, and decreased growth of the epitaxy in a second direction substantially perpendicular to the first direction.

3. The method of claim 2, wherein the modifying comprises:

increasing an area of (100) surface orientation at a top of the epitaxy; and

growing additional epitaxy on the increased area.

4. The method of claim 3, wherein the increasing comprises annealing the epitaxy.

5. The method of claim 4, wherein the epitaxy comprises silicon, and wherein the annealing comprises annealing to a temperature of at least about 750°

C.

6. The method of claim 5, wherein the temperature comprises about 850°

C.

7. The method of claim 4, wherein the increasing and the growing additional epitaxy are performed in a same chamber.

8. The method of claim 3, further comprising a plurality of cycles of increasing the area of (100) surface orientation and growing additional epitaxy on the increased area.

9. The method of claim 1, wherein the semiconductor substrate comprises a bulk semiconductor substrate.

10. A semiconductor structure, comprising:

a semiconductor substrate;

a plurality of raised semiconductor structures coupled to the substrate; and

a plurality of shaped epitaxial structures of a semiconductor material on top surfaces of the plurality of raised semiconductor structures, wherein the shaped epitaxial structures on adjacent raised structures are separated by a space, and wherein the shaped structures are modified as compared to an initial cycle of epitaxial growth to have greater volume and greater space between adjacent shaped structures.

11. The semiconductor structure of claim 10, wherein the semiconductor material of the shaped epitaxial structures comprises silicon.

12. The semiconductor structure of claim 10, wherein the semiconductor material of the shaped epitaxial structures comprises Silicon-Germanium (SiGe).

13. The semiconductor structure of claim 10, wherein the semiconductor material of the shaped epitaxial structures comprises Germanium (Ge).

14. The semiconductor structure of claim 10, wherein the semiconductor material of the shaped epitaxial structures comprises Phosphorus doped Silicon Carbon (SiC:

P).

15. The semiconductor structure of claim 10, wherein the semiconductor material of the shaped epitaxial structures comprises Phosphorus doped Si.

16. A non-planar semiconductor transistor, comprising:

a semiconductor substrate;

a plurality of raised semiconductor structures coupled to the semiconductor substrate;

a source, a drain and a channel on a surface of the plurality of raised semiconductor structures opposite the semiconductor substrate, wherein the source, the drain and the channel comprise a plurality of shaped epitaxial structures of a semiconductor material; and

wherein the plurality of shaped epitaxial structures on adjacent raised structures are separated by a space, and wherein the shaped structures are modified as compared to an initial cycle of epitaxial growth to have greater volume and greater space between adjacent shaped structures.

17. The non-planar semiconductor transistor of claim 16, wherein the semiconductor substrate comprises a bulk silicon substrate, and wherein the semiconductor material of the shaped epitaxial structures comprises silicon.

18. The non-planar semiconductor transistor of claim 16, wherein the semiconductor substrate comprises a bulk silicon substrate, and wherein the semiconductor material of the shaped epitaxial structures comprises Silicon-Germanium (SiGe).

19. The non-planar semiconductor transistor of claim 16, wherein the semiconductor substrate comprises a bulk silicon substrate, and wherein the semiconductor material of the shaped epitaxial structures comprises Germanium (Ge).

20. The non-planar semiconductor transistor of claim 16, wherein the semiconductor substrate comprises a bulk silicon substrate, and wherein the semiconductor material of the shaped epitaxial structures comprises one of Phosphorus doped Silicon Carbon (SiC:

P) and Phosphorus doped Si.