SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

• US 20150123231A1
• Filed: 11/06/2014
• Published: 05/07/2015
• Est. Priority Date: 11/07/2013
• Status: Active Grant

• Current Assignee: Xintec Incorporated
• Original Assignee: Xintec Incorporated
• Inventors: CHIEN, Wei-Ming, LEE, Po-Han, LIU, Tsang-Yu, HO, Yen-Shih
• Granted Patent: US 9,214,579 B2
• Time in Patent Office: Days
• US Class Current: 257/432
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/0348 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05582 Two-layer coating
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/113 by local deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 31/02002 : Arrangements for conducting electric current to or from the device in operations
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/02327 : the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216
• CPC Class Codes: H01L 31/02363 : of the semiconductor body itself, e.g. textured active layers
• CPC Class Codes: H01L 31/1804 : comprising only elements of Group IV of the Periodic Table

Abstract

A manufacturing method of a semiconductor structure includes the following steps. A wafer structure having a silicon substrate and a protection layer is provided. An electrical pad on the protection layer is exposed through the concave region of the silicon substrate. An isolation layer is formed on the sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer. A redistribution layer is formed on the isolation layer and the electrical pad. A passivation layer is formed on the redistribution layer. The passivation layer is patterned to form a first opening therein. A first conductive layer is formed on the redistribution layer exposed through the first opening. A conductive structure is arranged in the first opening, such that the conductive structure is in electrical contact with the first conductive layer.

Claims

1. A manufacturing method of a semiconductor structure, the manufacturing method comprising:

(a) providing a wafer structure having a silicon substrate and a protection layer, wherein an electrical pad on the protection layer is exposed through a concave region of the silicon substrate;

(b) forming an isolation layer on a sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer;

(c) forming a redistribution layer on the isolation layer and the electrical pad;

(d) forming a passivation layer on the redistribution layer;

(e) patterning the passivation layer to form a first opening therein, thereby exposing the redistribution layer on the surface of the silicon substrate through the first opening;

(f) forming a first conductive layer on the redistribution layer that is exposed through the first opening; and

(g) arranging a conductive structure in the first opening, thereby enabling the conductive structure to electrically contact the first conductive layer.

2. The manufacturing method of claim 1, wherein step (e) further comprises:

patterning the passivation layer to form a second opening therein, thereby exposing the redistribution layer on the electrical pad and the sidewall through the second opening.

3. The manufacturing method of claim 2, wherein step (f) further comprises:

forming a second conductive layer on the redistribution layer that is exposed through the second opening.

4. The manufacturing method of claim 1, wherein the first conductive layer in step (f) is formed by utilizing a chemical plating process.

5. The manufacturing method of claim 1, wherein the isolation layer in step (b) is formed by utilizing a chemical vapor deposition process.

6. The manufacturing method of claim 1, wherein the wafer structure has a light transmissive element and a supporting layer that is located between the light transmissive element and the protection layer, and the manufacturing method further comprises:

cutting the passivation layer, the silicon substrate, the protection layer, the supporting layer, and the light transmissive element.

7. The manufacturing method of claim 1, further comprising:

forming a tooth structure in the silicon substrate, wherein a height of the tooth structure is smaller than or equal to a height of the surface of the silicon substrate.

8. A semiconductor structure, comprising:

a silicon substrate having a light sensor and a concave region;

a protection layer located on the silicon substrate and covering the light sensor;

an electrical pad located on the protection layer and aligned with the concave region;

an isolation layer located on a sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer;

a redistribution layer located on the isolation layer and the electrical pad;

a passivation layer located on the redistribution layer and having a first opening;

a first conductive layer located on the redistribution layer that is exposed through the first opening; and

a conductive structure located in the first opening and in electrical contact with the first conductive layer.

9. The semiconductor structure of claim 8, wherein the passivation layer has a second opening, and the redistribution layer located on the electrical pad and the sidewall is exposed through the second opening.

10. The semiconductor structure of claim 9, further comprising:

a second conductive layer located on the redistribution layer that is exposed through the second opening.

11. The semiconductor structure of claim 10, wherein a perpendicular height of the second conductive layer is smaller than a perpendicular height of the surface of the silicon substrate.

12. The semiconductor structure of claim 8, wherein a caliber of the concave region is gradually increased toward the electrical pad, such that the sidewall of the silicon substrate is an oblique surface.

13. The semiconductor structure of claim 8, wherein the isolation layer is made of a material comprising oxide or nitride.

14. The semiconductor structure of claim 8, further comprising:

a light transmissive element; and

a supporting layer between the light transmissive element and the protection layer.

15. The semiconductor structure of claim 8, wherein the silicon substrate further comprises:

a tooth structure adjacent to the concave region, wherein a height of the tooth structure is smaller than or equal to a height of the surface of the silicon substrate, and a top end of the tooth structure is cusp-shaped, round-shaped, or flat-shaped.

16. The semiconductor structure of claim 8, wherein the conductive structure is a solder ball or a conductive protruding block.