RECONFIGURABLE CIRCUIT, STORAGE DEVICE, AND ELECTRONIC DEVICE INCLUDING STORAGE DEVICE

• US 20150123704A1
• Filed: 10/29/2014
• Published: 05/07/2015
• Est. Priority Date: 11/01/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Granted Patent: US 9,515,656 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: H03K 19/00392 by circuit redundancy H03K19/0075 takes precedence
• CPC Class Codes: H03K 19/0075 by using two redundant chains
• CPC Class Codes: H03K 19/017581 programmable
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H03K 19/21 EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical

Abstract

A reconfigurable circuit suitable for a redundant circuit of a storage device is provided. A programmable logic element (PLE) includes k logic circuits (e.g., XNOR circuits), k configuration memories (CM), and another logic circuit (e.g., an AND circuit) to which the outputs of the k logic circuits are input. The output of the AND circuit represents whether k input data of the PLE all correspond to configuration data stored in the k CMs. For example, when the address of a defective block in the storage device is stored in the CM and address data of the storage device the access of which is requested is input to the PLE, whether the defective block is accessible can be determined from the output of the AND circuit.

Claims

1. A reconfigurable circuit comprising:

at least one programmable logic element, the programmable logic element comprising;

first to k-th logic circuits, where k is an integer of two or more;

first to k-th configuration memories;

a programmable look-up table;

a register; and

a multiplexer,

wherein the register is configured to store data output from the programmable look-up table,

wherein the multiplexer is configured to select and output data output from the programmable look-up table or data output from the register,

wherein the first to k-th logic circuits are each configured to perform an operation of an exclusive-NOR of first to k-th data and first to k-th configuration data output from the first to k-th configuration memories, respectively, and output an operation result as (k+1)th to 2k-th data, and

wherein the programmable look-up table is configured to perform a logical operation of the (k+1)th to 2k-th data and (2k+1)th data and output an operation result as (2k+2)th data.

2. The reconfigurable circuit according to claim 1,

wherein in the h programmable logic elements, where h is an integer of two or more, the h programmable look-up tables are cascaded, and

wherein the (2k+2)th data output from the h programmable look-up tables are configured to be input as the (2k+1)th data of the programmable look-up table in the next stage.

3. A reconfigurable circuit comprising:

at least one programmable logic element, the programmable logic element comprising;

first to (k+1)th logic circuits, where k is an integer of two or more;

first to k-th configuration memories;

a programmable look-up table;

a register; and

a multiplexer,

wherein the register is configured to store data output from the programmable look-up table,

wherein the multiplexer is configured to select and output data output from the programmable look-up table or data output from the register,

wherein the first to k-th logic circuits are each configured to perform an operation of an exclusive-NOR of first to k-th data and first to k-th configuration data output from the first to k-th configuration memories, respectively, and output an operation result as (k+1)th to 2k-th data,

wherein the (k+1)th logic circuit is configured to perform a logical operation of the (k+1)th to 2k-th data and (2k+1)th data and output an operation result as (2k+2)th data, and

wherein the (k+1)th to 2k-th data are configured to be input to the programmable look-up table.

4. The reconfigurable circuit according to claim 3,

wherein in the h programmable logic elements, where h is an integer of two or more, the (k+1)th h logic circuits are cascaded, and

wherein the (2k+2)th data output from the (k+1)th h logic circuits are configured to be input as the (2k+1)th data of the (k+1)th logic circuit in the next stage.

5. The reconfigurable circuit according to claim 3, wherein the (k+1)th logic circuit is an AND circuit.

6. A storage device comprising:

a memory portion comprising a memory cell array comprising a plurality of memory cells; and

a redundant circuit,

wherein the memory portion comprises;

the memory cell array where the plurality of memory cells are arranged; and

a peripheral circuit configured to select at least one of the memory cells specified by a logical address and to read and write data,

wherein the memory cell array comprises;

a first storage area including 2ⁿ blocks, where n is an integer of one or more; and

a second storage area including m redundant blocks, where m is an integer, 1≦

m<

2ⁿ, to be substituted for defective blocks where defective memory cells exit in the first storage area,

wherein higher-order m bits are configured to function as redundant addresses in physical addresses of the first and second storage areas,

wherein physical addresses of the 2ⁿ blocks each have a structure where a redundant address is added to a higher-order bit of the logical address,

wherein redundant addresses of the 2ⁿ blocks are the same,

wherein redundant addresses of the m redundant blocks are different from each other and different from a redundant address of the first storage area,

wherein the redundant circuit includes a memory configured to store a logical address of the defective block in the first storage area and generates the redundant address from a logical address stored in the memory and a logical address of the second storage area the access of which is requested, and

wherein when a redundant address generated in the redundant circuit agrees with any of the redundant addresses of the m redundant blocks, the peripheral circuit is configured to select the redundant block.

7. The storage device according to claim 6,

wherein the redundant circuit is reconfigurable to produce data for testing the memory portion,

wherein when the first storage area is tested, the redundant circuit outputs at least a logical address of the block to be tested to the peripheral circuit as test data, and

wherein when the second storage area is tested, the redundant circuit outputs the redundant address of the redundant block to the peripheral circuit as test data.

8. The storage device according to claim 6, wherein the redundant circuit is a reconfigurable circuit comprising:

at least one programmable logic element, the programmable logic element comprising;

first to k-th logic circuits, where k is an integer of two or more;

first to k-th configuration memories;

a programmable look-up table;

a register; and

a multiplexer,

wherein the register is configured to store data output from the programmable look-up table,

wherein the multiplexer is configured to select and output data output from the programmable look-up table or data output from the register,

wherein the first to k-th logic circuits are each configured to perform an operation of an exclusive-NOR of first to k-th data and first to k-th configuration data output from the first to k-th configuration memories, respectively, and output an operation result as (k+1)th to 2k-th data, and

wherein the programmable look-up table is configured to perform a logical operation of the (k+1)th to 2k-th data and (2k+1)th data and output an operation result as (2k+2)th data.

9. The storage device according to claim 6, wherein the redundant circuit is a reconfigurable circuit comprising:

at least one programmable logic element, the programmable logic element comprising;

first to (k+1)th logic circuits, where k is an integer of two or more;

first to k-th configuration memories;

a programmable look-up table;

a register; and

a multiplexer,

wherein the register is configured to store data output from the programmable look-up table,

wherein the multiplexer is configured to select and output data output from the programmable look-up table or data output from the register,

wherein the first to k-th logic circuits are each configured to perform an operation of an exclusive-NOR of first to k-th data and first to k-th configuration data output from the first to k-th configuration memories, respectively, and output an operation result as (k+1)th to 2k-th data,

wherein the (k+1)th logic circuit is configured to perform a logical operation of the (k+1)th to 2k-th data and (2k+1)th data and output an operation result as (2k+2)th data, and

wherein the (k+1)th to 2k-th data are configured to be input to the programmable look-up table.

10. An electronic device comprising the storage device according to claim 6.