SERIALIZERS

• US 20150123826A1
• Filed: 02/10/2014
• Published: 05/07/2015
• Est. Priority Date: 11/06/2013
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: LEE, Sang Kwon, LEE, Hyeng Ouk
• Granted Patent: US 9,100,029 B2
• Time in Patent Office: Days
• US Class Current: 341/101
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00

Abstract

Serializers are provided. The serializer includes a first drive control signal generator and a second drive control signal generator. The first drive control signal generator amplifies a first input data signal in response to a first clock signal and a second clock signal to generate a first pull-up drive control signal and a first pull-down drive control signal. The second drive control signal generator amplifies a second input data signal in response to the second clock signal and a third clock signal to generate a second pull-up drive control signal and a second pull-down drive control signal.

Claims

1. A serializer comprising:

a first drive control signal generator suitable for amplifying a first input data signal in response to a first clock signal and a second clock signal to generate a first pull-up drive control signal and a first pull-down drive control signal; and

a second drive control signal generator suitable for amplifying a second input data signal in response to the second clock signal and a third clock signal to generate a second pull-up drive control signal and a second pull-down drive control signal.

2. The serializer of claim 1, wherein the first clock signal precedes the second clock signal by a set phase.

3. The serializer of claim 1, wherein the first clock signal precedes the second clock signal by a phase of about 90 degrees.

4. The serializer of claim 3, wherein the first drive control signal generator amplifies the first input data while the first and second clock signals have a predetermined logic level combination.

5. The serializer of claim 3, wherein the second clock signal precedes the third clock signal by a phase of about 90 degrees.

6. The serializer of claim 5, wherein the second drive control signal generator amplifies the second input data while the second and third clock signals have a predetermined logic level combination.

7. The serializer of claim 1, further comprising an output drive signal generator suitable for buffering the first pull-up drive control signal or the second pull-up drive control signal to generate an output pull-up drive signal, suitable for buffering the first pull-down drive control signal or the second pull-down drive control signal to generate an output pull-down drive signal, and suitable for latching the output pull-up drive signal and the output pull-down drive signal.

8. The serializer of claim 7, further comprising a driver suitable for driving an output data signal in response to the output pull-up drive signal and the output pull-down drive signal.

9. The serializer of claim 1, wherein the first drive control signal generator includes an initialization unit suitable for receiving the first clock signal and the second clock signal to initialize a first node through which a latch signal is outputted and a second node through which a complementary latch signal is outputted.

10. The serializer of claim 9, wherein the first drive control signal generator further includes a discharge unit suitable for receiving the first input data signal in response to the first clock signal and the second clock signal to discharge electric charges of the first node or the second node.

11. The serializer of claim 10, wherein the discharge unit selectively discharges the electric charges of one of the first node and the second node according to a logic level of the first input data signal while the first and second clock signals have a predetermined logic level combination.

12. The serializer of claim 10, wherein the first drive control signal generator further includes a charge supply unit suitable for selectively supplying electric charges to one of the first and second nodes according to logic levels of the first and second nodes.

13. The serializer of claim 12, wherein the first drive control signal generator further includes a signal output unit suitable for outputting the first pull-up drive control signal and the first pull-down drive control signal, any one of which is selectively driven according to logic levels of the latch signal and the complementary latch signal.

14. The serializer of claim 1, wherein the first drive control signal generator comprises:

an initialization unit suitable for receiving the first clock signal and the second clock signal to initialize a first node through which a latch signal is outputted and a second node through which a complementary latch signal is outputted;

a discharge unit suitable for receiving the first input data signal in response to the first clock signal and the second clock signal to discharge electric charges of the first node or the second node; and

a charge supply unit suitable for selectively supplying electric charges to one of the first and second nodes according to logic levels of the first and second nodes.

15. A serializer comprising:

an initialization unit suitable for receiving a first clock signal and a second clock signal to initialize a first node through which a latch signal is outputted and a second node through which a complementary latch signal is outputted;

a discharge unit suitable for receiving an input data signal in response to the first clock signal and the second clock signal to discharge electric charges of the first node or the second node; and

a charge supply unit suitable for selectively supplying electric charges to one of the first and second nodes according to logic levels of the first and second nodes.

16. The serializer of claim 15, wherein the first clock signal precedes the second clock signal by a phase of about 90 degrees.

17. The serializer of claim 15, wherein the discharge unit selectively discharges electric charges of one of the first node and the second node according to a logic level of the input data signal while the first and second clock signals have a predetermined logic level combination.

18. The serializer of claim 15, further comprising a signal output unit configured for outputting a pull-up drive control signal and a pull-down drive control signal, any one of which is selectively driven according to logic levels of the latch signal and the complementary latch signal,

wherein the pull-up drive control signal and the pull-down drive control signal are generated to selectively drive an output data signal.

19. A serializer comprising:

an initialization unit configured for receiving a first clock signal and a second clock signal to initialize a first node through which a latch signal is outputted and a second node through which a complementary latch signal is outputted; and

a signal output unit configured for outputting a pull-up drive control signal and a pull-down drive control signal, any one of which is selectively driven according to logic levels of the latch signal and the complementary latch signal,

wherein the pull-up drive control signal and the pull-down drive control signal are generated to selectively drive an output data signal.

20. The serializer of claim 19, wherein the first clock signal precedes the second clock signal by a set phase.