WAVEGUIDE FORMATION USING CMOS FABRICATION TECHNIQUES

• US 20150125111A1
• Filed: 10/22/2014
• Published: 05/07/2015
• Est. Priority Date: 10/22/2013
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Ram, Rajeev Jagga, Orcutt, Jason Scott, Mehta, Karan Kartik, Atabaki, Amir Hossein
• Granted Patent: US 9,529,150 B2
• Time in Patent Office: Days
• US Class Current: 385/14
• CPC Class Codes: G01N 21/7703 using reagent-clad optical fibres or optical waveguides using measurement of total internal reflection or attenuated total reflection G01N21/552; optical fibres or waveguides per se G02B
• CPC Class Codes: G01N 21/7746 the waveguide coupled to a cavity resonator
• CPC Class Codes: G02B 2006/12061 Silicon
• CPC Class Codes: G02B 2006/12097 Ridge, rib or the like
• CPC Class Codes: G02B 2006/121 Channel; buried or the like
• CPC Class Codes: G02B 2006/12107 Grating
• CPC Class Codes: G02B 2006/12123 Diode
• CPC Class Codes: G02B 6/12004 Combinations of two or more optical elements
• CPC Class Codes: G02B 6/122 Basic optical elements, e.g. light-guiding paths
• CPC Class Codes: G02B 6/1225 comprising photonic band-gap structures or photonic lattices
• CPC Class Codes: G02B 6/132 by deposition of thin films
• CPC Class Codes: G02B 6/136 by etching
• CPC Class Codes: G02B 6/305 and having an integrated mode-size expanding section, e.g. tapered waveguide
• CPC Class Codes: G02F 1/0147 based on thermo-optic effects G02F1/132 takes precedence
• CPC Class Codes: G02F 1/0151 modulating the refractive index
• CPC Class Codes: G02F 1/025 in an optical waveguide structure G02F1/017, G02F1/2257 take precedence

Abstract

Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer. Filling the trench with a high-index dielectric material yields a waveguide that can guide visible and/or infrared light, depending on the waveguide'"'"'s dimensions and refractive index contrast.

Claims

1. A method of making at least one optical waveguide in a silicon substrate having a front side, a back side, and at least one ridge extending from the front side of the silicon substrate and a dielectric layer of first dielectric material deposited on the front side of the silicon substrate over the at least one ridge, the first dielectric material having a first refractive index, the method comprising:

(A) etching a portion of the back side of the silicon substrate so as to form at least one trench in the dielectric layer via removal of the at least one ridge extending from the front side of the silicon substrate; and

(B) depositing a waveguide core material, having a second refractive index greater than the first refractive index, into the at least one trench so as to form a core of the at least one optical waveguide.

2. The method of claim 1, wherein:

the silicon substrate comprises a first electronic device and a second electronic device formed in the silicon substrate, and

(A) comprises removing silicon disposed between the first electronic device and the second electronic device so as to form the at least one trench in the dielectric layer.

3. The method of claim 2, wherein (A) further comprises defining a path for the optical waveguide between the first electronic device and the second electronic device.

4. The method of claim 3, wherein:

the dielectric layer extends at least partially between the first electronic device and the second electronic device, and

(A) further comprises etching the at least one trench to extend at least partially into a plane containing the first electronic device and the second electronic device.

5. The method of claim 2, wherein at least one of the first electronic device and the second electronic device comprises at least one of a transistor, a photodetector, a modulator, and a light source.

6. The method of claim 1, wherein (A) comprises at least one of vapor phase etching, wet etching, deep reactive ion etching, and multi-step etching.

7. The method of claim 1, wherein (A) comprises etching the at least one trench to a width of less than or equal to about 130 nm.

8. The method of claim 7, wherein (A) comprises etching the width of the at least one trench to a precision of less than or equal to about 1 nm.

9. The method of claim 1, wherein:

(A) comprises exposing a portion of the dielectric layer, through the silicon substrate, adjacent to the at least one trench; and

(B) comprises depositing a uniform layer of the waveguide core material over at least a portion of the dielectric layer adjacent to the at least one trench.

10. The method of claim 1, wherein (B) comprises depositing at least one of polymer, amorphous silicon, silicon nitride, silicon-rich silicon nitride, aluminum nitride, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, and amorphous silicon germanium alloy in the at least one trench.

11. The method of claim 1, further comprising, before (B):

depositing a second dielectric material, within the dielectric layer beneath the at least one trench or within the at least one trench, to form a cladding layer of the at least one waveguide.

12. The method of claim 1, wherein the waveguide core material is at least partially transparent at at least one wavelength in a range from about 400 nm to about 2000 nm.

13. The method of claim 1, further comprising:

(C) etching away at least a portion of the waveguide core material; and

(D) depositing a cladding layer on the waveguide core material etched in (C).

14. The method of claim 1, further comprising:

forming a heater, in thermal communication with the core of the optical waveguide, to heat the optical waveguide so as to vary the second refractive index.

15. A semiconductor device comprising:

a silicon substrate having a front side and a back side and defining a recess extending through the silicon substrate from the back side of the silicon substrate to the front side of the silicon substrate;

a dielectric layer of first dielectric material, having a first refractive index, disposed on the front side of the silicon substrate, the dielectric layer defining a trench open to the recess defined by the silicon substrate; and

an optical waveguide comprising a second dielectric material, having a second refractive index greater than the first refractive index, disposed within the trench.

16. The semiconductor device of claim 15, wherein the first dielectric material comprises at least one of silicon dioxide, silicon nitride, and silicon oxynitride.

17. The semiconductor device of claim 15, wherein the second dielectric material comprises at least one of polymer, amorphous silicon, silicon nitride, silicon-rich silicon nitride, aluminum oxide, polycrystalline silicon, amorphous silicon germanium, polycrystalline silicon germanium, amorphous silicon carbide, polycrystalline silicon carbide, titanium oxide, tantalum oxide, zinc oxide, and silicon oxynitride.

18. The semiconductor device of claim 15, wherein the second dielectric material is at least partially transparent at at least one wavelength in a range from about 400 nm to about 2000 nm.

19. The semiconductor device of claim 15, wherein the trench has a width of less than or equal to about 130 nm.

20. The semiconductor device of claim 15, further comprising:

a layer of the second dielectric material disposed within the recess over at least a portion of the dielectric layer adjacent to the trench.

21. The semiconductor device of claim 15, further comprising:

a cladding layer, disposed over at least a portion of the optical waveguide, to protect the second dielectric material.

22. The semiconductor device of claim 15, further comprising:

a third dielectric material, disposed within the dielectric layer beneath the trench or within the trench, to form a cladding layer for the optical waveguide.

23. The semiconductor device of claim 15, further comprising:

a first electronic device formed in the silicon substrate on a first side of the recess;

a second electronic device formed in the silicon substrate on a second side of the recess, and

wherein the optical waveguide defines an optical path between the first electronic device and the second electronic device.

24. The semiconductor device of claim 23, wherein:

the dielectric layer extends at least partially between the first electronic device and the second electronic device, and

the optical waveguide extends at least partially along a plane containing the first electronic device and the second electronic device.

25. The semiconductor device of claim 24, wherein at least one of the first electronic device and the second electronic device comprises at least one of a transistor, a photodetector, a modulator, and a light source.

26. The semiconductor device of claim 15, further comprising:

a heater, in thermal communication with the optical waveguide, to heat the optical waveguide so as to change the second refractive index.

27. The semiconductor device of claim 15, further comprising:

a grating structure, defined in the optical waveguide, to diffract light into and/or out of the optical waveguide.

28. The semiconductor device of claim 15, further comprising:

a resonator, in evanescent communication with the optical waveguide, to resonate in response to light propagating via the optical waveguide.

29. The semiconductor device of claim 15, further comprising:

another optical waveguide, in evanescent communication with the optical waveguide, to guide light coupled into and/or out of the optical waveguide from the other optical waveguide.

30. The semiconductor device of claim 15, further comprising:

an electrical contact, in electrical communication with the optical waveguide, to apply an electrical signal to the optical waveguide.

31. A method of making at least one optical waveguide in a silicon substrate having a front side, a back side, and a first refractive index, the method comprising:

(A) etching the front side of the silicon substrate so as to define a silicon ridge on the front side of the silicon substrate;

(B) depositing a layer of dielectric material having a second refractive index lower than the first refractive index on the ridge and on at least a portion of the front side of the silicon substrate adjacent to the silicon ridge; and

(C) etching a portion of the back side of the silicon substrate so as to expose a portion of the silicon ridge through the silicon substrate from the back side of the silicon substrate.

32. The method of claim 31, wherein (A) comprises defining the silicon ridge to have a width of about 250 nm or less.

33. The method of claim 31, wherein (C) comprises chemically-mechanically polishing the back side of the silicon substrate.

34. The method of claim 31, further comprising, before (C):

defining a pn junction in the silicon ridge.

35. The method of claim 31, wherein (C) comprises:

electro-chemically etching the back side of the silicon substrate to the pn junction.

36. A semiconductor device comprising:

a silicon substrate having a front side, a back side, and a first refractive index, and defining a recess extending through the silicon substrate from the back side of the silicon substrate to the front side of the silicon substrate;

a dielectric layer of first dielectric material, having a second refractive index lower than the first refractive index, disposed on the front side of the silicon substrate, the dielectric layer defining a trench open to the recess defined by the silicon substrate; and

silicon disposed within the trench to form a core of an optical waveguide.

37. The semiconductor device of claim 36, wherein the trench has a width of about 250 nm or less.

38. The semiconductor device of claim 36, further comprising:

a pn junction formed in the silicon disposed within the trench.