METHOD FOR SEPARATING SEMICONDUCTOR DEVICES USING NANOPOROUS STRUCTURE

• US 20150125981A1
• Filed: 02/06/2013
• Published: 05/07/2015
• Est. Priority Date: 02/06/2012
• Status: Active Grant

• Current Assignee: University Industry Liaison Office of Chonnam National University
• Original Assignee: Seoul Viosys Co., Ltd. (Seoul Semiconductor Co., Ltd.), University Industry Liaison Office of Chonnam National University
• Inventors: Ryu, Sang Wan, Kang, Jin Ho
• Granted Patent: US 9,356,187 B2
• Time in Patent Office: Days
• US Class Current: 438/47
• CPC Class Codes: H01L 21/76259 with separation/delamination along a porous layer
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/32 containing nitrogen

Abstract

The present invention relates to a method for separating semiconductor devices from a substrate using a nanoporous structure, wherein electrochemical etching is carried out in the absence of a surface metal layer, then the surface metal layer is deposited, and then a GaN thin film is transferred onto a metal wafer by means of wafer bonding and lift-off. The method for separating the semiconductor devices using a nanoporous structure includes the steps of: growing a first n-type nitride layer on the substrate; growing a dielectric layer on the first n-type nitride layer; forming a nanoporous structure in the first n-type nitride layer by means of electrochemical etching; re-growing a second n-type nitride layer on the first n-type nitride layer so as to form a second n-type nitride layer containing the dielectric layer; growing a multi-quantum well structure and a p-type nitride layer on the second n-type nitride layer for bonding with a conductive substrate; and separating the semiconductor devices from the substrate through selective HF etching of the dielectric layer.

Claims

1. A method for separating semiconductor devices from a substrate using a nanoporous structure, the method comprising:

forming a first conductivity-type nitride layer on a substrate;

forming a dielectric layer on the first conductivity-type nitride layer;

forming a nanoporous structure in the first conductivity-type nitride layer using electrolytic etching;

forming a second first conductivity-type nitride layer on the first conductivity-type nitride layer and the dielectric layer;

forming a multi-quantum well structure and a second conductivity-type nitride layer on the second first conductivity-type nitride layer;

bonding the multi-quantum well structure and the second conductivity-type nitride layer to a conductive substrate; and

separating the second first conductivity-type nitride layer from the substrate by selectively etching the dielectric layer using HF.

2. The method of claim 1, wherein the dielectric layer comprises SiO₂ or SiN_x.

3. The method of claim 1, wherein forming the dielectric layer comprises forming the dielectric layer in a stripe pattern or a lattice pattern, and the dielectric layer formed at an edge of the substrate is connected to the dielectric layer formed on an inner area of the substrate.

4. The method of claim 1, wherein forming the dielectric layer comprises nano-patterning, the nano-patterning comprising at least one of aluminum anodizing, laser holography patterning, and nanoparticle coating.

5. The method of claim 1, wherein forming the nanoporous structure comprises forming the nanoporous structure within the first n-type nitride layer such that an upper portion of the nanoporous structure has a low porosity and a lower portion of the nanoporous structure has a high porosity by setting an initial voltage to a low value, followed by increasing the voltage after a predetermined period of time, at the same doping concentration.

6. A method for separating semiconductor devices from a substrate using a nanoporous structure, the method comprising:

forming a first conductivity-type nitride layer on a substrate;

forming a dielectric layer on the first conductivity-type nitride layer such that a pattern pitch of the dielectric layer corresponds to a semiconductor chip size;

forming a nanoporous structure in the first conductivity-type nitride layer using through electrolytic etching;

forming a second first conductivity-type nitride layer on the first conductivity-type nitride layer;

forming a multi-quantum well structure and a second conductivity-type nitride layer on the second first conductivity-type nitride layer;

bonding the multi-quantum well structure and the second conductivity-type nitride layer to a conductive substrate; and

separating the second first conductivity-type nitride layer from the substrate by selectively etching the dielectric layer using HF.

7. The method of claim 6, wherein the dielectric layer comprises SiO₂ or SiN_x.

8. The method of claim 6, wherein forming the dielectric layer comprises nano-patterning, the nano-patterning comprising at least one of aluminum anodizing, laser holography patterning, and nanoparticle coating.

9. The method of claim 6, wherein forming the nanoporous structure comprises forming the nanoporous structure within the first n-type nitride layer such that an upper portion of the nanoporous structure has a low porosity and a lower portion of the nanoporous structure has a high porosity by setting an initial voltage to a low value, followed by increasing the voltage after a predetermined period of time, at the same doping concentration.