SERDES RECEIVER OVERSAMPLING RATE

• US 20150127877A1
• Filed: 11/04/2013
• Published: 05/07/2015
• Est. Priority Date: 11/04/2013
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Novellini, Paolo, Torza, Anthony
• Granted Patent: US 9,378,174 B2
• Time in Patent Office: Days
• US Class Current: 710/316
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver

Abstract

An apparatus relates generally to serializer-deserializers. In such an apparatus, a first serializer-deserializer has a first data path and a data eye path. The first data path is coupled to a first data out interface of the first serializer-deserializer. A second serializer-deserializer has a second data path. The second data path is coupled to a second data out interface of the second serializer-deserializer. The data eye path of the first serializer-deserializer is coupled to the second data path of the second serializer-deserializer.

Claims

1. An apparatus, comprising:

a first serializer-deserializer;

wherein the first serializer-deserializer has a first data path and a data eye path;

wherein the first data path is coupled to a first data out interface of the first serializer-deserializer;

a second serializer-deserializer;

wherein the second serializer-deserializer has a second data path;

wherein the second data path is coupled to a second data out interface of the second serializer-deserializer; and

wherein the data eye path of the first serializer-deserializer is coupled to the second data path of the second serializer-deserializer.

2. The apparatus according to claim 1, wherein:

the data eye path is a first data eye path; and

the second serializer-deserializer has a second data eye path.

3. The apparatus according to claim 1, further comprising:

a first delay coupled to the first data out interface;

a second delay coupled to the second data out interface; and

wherein at least one of the first delay and the second delay is adjustable relative to one another for skew adjustment between first information on the first data out interface and second information on the second data out interface.

4. The apparatus according to claim 3, further comprising:

an interleaver coupled to the first delay and the second delay to interleave the first information and the second information to provide interleaved information; and

an aligner coupled to the interleaver to receive the interleaved information.

5. The apparatus according to claim 4, wherein the aligner is coupled to at least one of the first delay and the second delay to provide an adjustment increment thereto for the skew adjustment between the first information on the first data out interface and the second information on the second data out interface.

6. The apparatus according to claim 3, wherein:

the first delay is a fixed delay; and

the second delay is adjustable for the skew adjustment between the first information on the first data out interface and the second information on the second data out interface.

7. The apparatus according to claim 3, wherein the first delay and the second delay are both adjustable for the skew adjustment in only one direction between the first information on the first data out interface and the second information on the second data out interface.

8. The apparatus according to claim 4, wherein some or all of each of the first delay, the second delay, the interleaver, and the aligner are instantiated in programmable resources.

9. The apparatus according to claim 4, wherein the programmable resources are of a Field Programmable Gate Array device.

10. The apparatus according to claim 1, wherein the first data out interface and the second data out interface are for coupling to an array of programmable resources.

11. The apparatus according to claim 10, wherein the array of programmable resources is of a Field Programmable Gate Array device.

12. The apparatus according to claim 1, wherein the data eye path is a non-destructive path with respect to the data path.

13. The apparatus according to claim 1, wherein the data eye path is not coupled to the first data out interface.

14. The apparatus according to claim 1, wherein the data eye path of the first serializer-deserializer is coupled to the second data path of the second serializer-deserializer through a multiplexer of the second serializer-deserializer.

15. The apparatus according to claim 14, wherein the multiplexer is in a hard physical coding sublayer (“

PCS”

) logic block of the second serializer-deserializer.

16. A method, comprising:

receiving first serial information to a first serializer-deserializer at a line rate;

oversampling the first serial information on each of a first data path and a data eye path of the first serializer-deserializer to respectively provide first parallel information and second parallel information;

wherein the first data path is coupled to a first data out interface of the first serializer-deserializer;

outputting the first parallel information via the first data out interface;

providing the second parallel information from the data eye path of the first serializer-deserializer to a second data path of a second serializer-deserializer;

wherein the second data path is coupled to a second data out interface of the second serializer-deserializer; and

outputting the second parallel information via the second data out interface.

17. The method according to claim 16, wherein each of the first parallel information and the second parallel information is oversampled at one-half of an effective oversampling rate.

18. The method according to claim 16, further comprising interleaving the first parallel information with the second parallel information to provide interleaved information.

19. The method according to claim 18, further comprising:

determining an adjustment amount for skew between the first parallel information and the second parallel information in the interleaved information; and

adjusting delay of at least one of the first parallel information and the second parallel information by the adjustment amount to reduce the skew.

20. The method according to claim 18, wherein the first data out interface and the second data out interface are for coupling to an array of programmable resources.