NONVOLATILE MEMORY SYSTEM

• US 20150127889A1
• Filed: 04/18/2013
• Published: 05/07/2015
• Est. Priority Date: 05/03/2012
• Status: Abandoned Application

• Current Assignee: THE-Aio., Ltd.
• Original Assignee: The-Aio Inc.
• Inventors: Hwang, Sun-Mo
• Application Number:
  US14/398,009
• Publication Number:
  US 20150127889A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A non-volatile memory system includes a NAND flash memory device including a first flash translation layer that performs a garbage collection operation, and a host device including a file system and a second flash translation layer that controls an operation of the NAND flash memory device by interacting with the file system. Here, the host device provides application data in an in-ordered form to the NAND flash memory device. Thus, the non-volatile memory system can perform a random write operation at high speed, and can minimize power consumption due to unnecessary data transfer.

Claims

1. A non-volatile memory system, comprising:

a NAND flash memory device including a first flash translation layer that performs a garbage collection operation; and

a host device including a file system and a second flash translation layer that controls an operation of the NAND flash memory device by interacting with the file system,

wherein the host device provides application data in an in-ordered form to the NAND flash memory device.

2. The system of claim 1, wherein the garbage collection operation that is performed by the first flash translation layer includes at least one selected among a merging operation, a compaction operation, and a wear-leveling operation.

3. The system of claim 2, wherein the second flash translation layer of the host device provides the application data in the in-ordered form.

4. The system of claim 2, wherein the file system of the host device provides the application data in the in-ordered form.

5. The system of claim 2, wherein the NAND flash memory device performs an in-ordered write operation for a target data block in response to an in-ordered write command when the host device outputs the in-ordered write command indicating the target data block to the NAND flash memory device.

6. The system of claim 5, wherein when a target page to be updated exists among valid pages included in the target data block, the NAND flash memory device, the NAND flash memory device programs an update page for the target page after copying the valid pages preceding the target page into a log block associated with the target data block.

7. The system of claim 2, wherein the NAND flash memory device performs the garbage collection operation for a target data block in response to a block deactivation command when the host device outputs the block deactivation command indicating the target data block to the NAND flash memory device.

8. The system of claim 7, wherein a log block is not assigned to a new data block until the host device outputs an in-ordered write command indicating the new data block, the new data block being generated by completing the garbage collection operation.

9. The system of claim 2, wherein the host device outputs a device information request command to the NAND flash memory device when the host device is first connected to the NAND flash memory device.

10. The system of claim 9, wherein when the host device outputs the device information request command to the NAND flash memory device, the NAND flash memory device outputs device information to the host device, and the host device stores the device information output from the NAND flash memory device.