SYSTEM AND MEMORY CONTROLLER FOR INTERRUPTIBLE MEMORY REFRESH

• US 20150127898A1
• Filed: 11/07/2013
• Published: 05/07/2015
• Est. Priority Date: 11/07/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cordero, Edgar R., Henderson, Joab D., Hovis, William P., Sabrowski, Jeffrey A., Saetow, Anuwat, Sethuraman, Saravanan, Fernandez, Carlos A.
• Granted Patent: US 10,096,353 B2
• Time in Patent Office: Days
• US Class Current: 711/106
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G11C 11/40603 Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays

Abstract

A refresh command is communicated to a memory device to initiate an interruptible refresh which contains multiple segment refreshes separated by interrupt boundaries. A command is communicated to the memory device before execution of a segment refresh and the segment refresh is delayed at an interrupt boundary. Alternatively, a first number of commands in a queue is determined. A first number of segment refreshes to execute is determined based on the first number of commands. The first number of segment refreshes to execute is communicated to the memory device to cause execution of the first number of segment refreshes. A second number of commands in the queue is determined. A second number of segment refreshes to execute is determined based on the second number of commands. The second number of segment refreshes to execute is communicated to the memory device to cause execution of the second number of segment refreshes.

Claims

1. A method for refreshing a memory device performed by a memory controller, the method comprising:

communicating a refresh command to the memory device, the refresh command configured to initiate an interruptible refresh by the memory device, the interruptible refresh comprising a plurality of segment refreshes, the plurality of segment refreshes separated by interrupt boundaries; and

communicating a first command to the memory device before execution of a first segment refresh, the first command configured to cause the memory device to execute the first command and delay execution of the first segment refresh at a first interrupt boundary.

2. The method of claim 1, wherein the communicating the first command to the memory device occurs at the first interrupt boundary.

3. The method of claim 1, further comprising:

determining to communicate the first command to the memory device.

4. The method of claim 3, wherein the determining to communicate the first command comprises:

determining that the first command is a high priority command.

5. The method of claim 3, further comprising:

determining a priority level for the first command; and

determining a first priority level for the interruptible refresh, wherein the determining to communicate the first command is based on the priority level of the first command and the first priority level of the interruptible refresh.

6. The method of claim 5, further comprising:

determining a priority for a second command;

determining a second priority for the interruptible refresh; and

determining not to communicate a second command to the memory device based on the priority for the second command and the second priority for the interruptible refresh and allowing a second segment refresh to execute after a second interrupt boundary.

7. The method of claim 1, further comprising:

determining a priority level for the interruptible refresh;

determining priority levels for one or more commands in a queue; and

determining that the priority level for the interruptible refresh is higher than the priority level for each of the one or more commands in the queue, wherein the communicating the refresh command occurs in response to the determining the priority level for the interruptible refresh is higher than the priority level for each of the one or more commands in the queue.

8. The method of claim 1, wherein the communicating the first command to the memory device occurs during execution of a second segment refresh, the second segment refresh occurring before the first segment refresh, the first command configured to cause the memory device to execute the first command at least partially simultaneously with the second segment refresh.

9. A system for refreshing a memory device, the system comprising:

a memory controller, the memory controller configured to communicate a refresh command to a memory device and to communicate a first command to the memory device before execution of a first segment refresh; and

a memory device, the memory device configured to;

initiate an interruptible refresh in response to the refresh command, the interruptible refresh comprising plurality of segment refreshes, the plurality of segment refreshes separated by interrupt boundaries; and

execute the first command and delay execution of the first segment refresh at a first interrupt boundary.

10. The system of claim 9, wherein the memory controller is configured to communicate the first command to the memory device at the first interrupt boundary.

11. The system of claim 9, wherein the memory controller is further configured to determine to communicate the first command to the memory device.

12. The system of claim 11, wherein the determining to communicate the first command comprises:

determining that the first command is a high priority command.

13. The system of claim 11, wherein the memory controller is further configured to:

determine a priority level for the first command; and

determine a first priority level for the interruptible refresh, wherein the determining to communicate the first command is based on the priority level of the first command and the first priority level of the interruptible refresh.

14. The system of claim 13, wherein the memory controller is further configured to:

determine a priority for a second command;

determine a second priority for the interruptible refresh; and

determine not to communicate a second command to the memory device based on the priority for the second command and the second priority for the interruptible refresh and not delay execution of a second segment refresh at a second interrupt boundary.

15. The system of claim 11, wherein the memory controller is further configured to allow the interruptible refresh to complete before expiration of a refresh interval.

16. The system of claim 9, wherein the memory controller is configured to communicate the first command to the memory device during execution of a second segment refresh, wherein the memory device is configured to execute the first command at least partially simultaneously with the second segment refresh.

17. A method for refreshing a memory device performed by a memory controller, the method comprising:

determining a first number of commands in a queue;

determining a first number of segment refreshes to execute based on the first number of commands, the first number of segment refreshes less than a total number of segment refreshes normally completed in a refresh interval.

communicating the determined first number of segment refreshes to execute to the memory device, the communication of the determined first number of segment refreshes to execute configured to cause the memory device to execute the first number of segment refreshes during the refresh interval;

determining a second number of commands in the queue;

determining a second number of segment refreshes to execute based on the second number of commands; and

communicating the determined second number of segment refreshes to execute to the memory device, the communication of the determined second number of segment refreshes to execute configured to cause the memory device to execute the second number of segment refreshes during the refresh interval.

18. The method of claim 17, wherein the first number of segment refreshes to execute is zero segment refreshes.

19. The method of claim 17, wherein the determining the first number of segment refreshes to execute and the second number of segment refreshes to execute is also based on one or more performance indicators.

20. The method of claim 17, further comprising:

communicating a command to the memory device, the command configured to execute at least partially simultaneously with one or more segment refreshes.