MEMORY DEVICE FOR INTERRUPTIBLE MEMORY REFRESH

• US 20150127899A1
• Filed: 11/07/2013
• Published: 05/07/2015
• Est. Priority Date: 11/07/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cordero, Edgar R., Fernandez, Carlos A., Henderson, Joab D., Hovis, William P., Sabrowski, Jeffrey A., Saetow, Anuwat, Sethuraman, Saravanan
• Granted Patent: US 9,972,376 B2
• Time in Patent Office: Days
• US Class Current: 711/106
• CPC Class Codes: G11C 11/40603 Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays

Abstract

A refresh command is received from a memory controller. An interruptible refresh containing multiple segment refreshes is initiated. The segment refreshes are separated by interrupt boundaries. A command is received before execution of a segment refresh. The first command is executed and execution of the first segment refresh is delayed at a first interrupt boundary. Alternatively, a first number of segment refreshes to execute is received from a memory controller. The received first number of segment refreshes is executed. A second number of segment refreshes to execute is received from a memory controller. The received second number of segment refreshes is executed. No segment refreshes are executed between the execution of the first number of segment refreshes and the execution of the second number of segment refreshes.

Claims

1. A method for refreshing a memory device performed by the memory device, the method comprising:

receiving a refresh command;

initiating an interruptible refresh in response to the refresh command, the interruptible refresh comprising a plurality of segment refreshes, the plurality of segment refreshes separated by interrupt boundaries;

receiving a first command before execution of a first segment refresh; and

executing the first command and delaying execution of the first segment refresh at a first interrupt boundary.

2. The method of claim 1, wherein the receiving the first command occurs at the first interrupt boundary.

3. The method of claim 2, further comprising:

determining that a second command was not received before execution of a second segment refresh; and

executing the second segment refresh without delay.

4. The method of claim 1, wherein the first command is received during execution of a second segment refresh, and wherein the first command is executed at least partially simultaneously with the execution of the second segment refresh.

5. The method of claim 1, wherein a size of the segment refreshes is determined based on size of the memory device.

6. The method of claim 1, wherein a size of the segment refreshes is determined for a particular workload.

19. The method of claim 1, wherein the communicating the first command to the memory device occurs during execution of a second segment refresh, the second segment refresh occurring before the first segment refresh, the first command configured to cause the memory device to execute the first command at least partially simultaneously with the second segment refresh.

7. A method for refreshing a memory device performed by the memory device, the method comprising:

receiving a first number of segment refreshes to execute from a memory controller, the first number of segment refreshes to execute less than a total number of segment refreshes normally completed in a refresh interval;

executing the received first number of segment refreshes;

receiving a second number of segment refreshes to execute from a memory controller; and

executing the received second number of segment refreshes, wherein no segment refreshes are executed between the execution of the first number of segment refreshes and the execution of the second number of segment refreshes.

8. The method of claim 7, wherein the first number of segment refreshes to execute is zero segment refreshes.

9. The method of claim 7, wherein a size of the segment refreshes is determined based on size of the memory device.

10. The method of claim 7, wherein a size of the segment refreshes is determined for a particular workload.

11. The method of claim 7, further comprising:

receiving a command; and

executing the command at least partially simultaneously with one or more segment refreshes.

12. A method for refreshing a memory device on a 3D stacked memory, performed by a logic chip on the 3D stacked memory, the method comprising:

receiving a first refresh command from a memory controller;

communicating a second refresh command to the memory device in response to receiving the first refresh command, the second refresh command configured to initiate an interruptible refresh by the memory device, the interruptible refresh comprising a plurality of segment refreshes, the plurality of segment refreshes separated by interrupt boundaries; and

communicating a first command to the memory device before execution of a first segment refresh, the first command configured to cause the memory device to execute the first command and delay execution of the first segment refresh at a first interrupt boundary.

13. The method of claim 12, wherein the communicating the first command to the memory device occurs at the first interrupt boundary.

14. The method of claim 12, further comprising:

determining to communicate the first command to the memory device.

15. The method of claim 14, wherein the determining to communicate the first command comprises:

determining that the first command is a high priority command.

16. The method of claim 14, further comprising:

determining a priority level for the first command; and

determining a first priority level for the interruptible refresh, wherein the determining to communicate the first command is based on the priority level of the first command and the first priority level of the interruptible refresh.

17. The method of claim 16, further comprising:

determining a priority for a second command;

determining a second priority for the interruptible refresh; and

determining not to communicate a second command to the memory device based on the priority for the second command and the second priority for the interruptible refresh and allowing a second segment refresh to execute after a second interrupt boundary.

18. The method of claim 12, further comprising:

determining a priority level for the interruptible refresh;

determining priority levels for one or more commands in a queue; and

determining that the priority level for the interruptible refresh is higher than the priority level for each of the one or more commands in the queue, wherein the communicating the second refresh command occurs in response to the determining the priority level for the interruptible refresh is higher than the priority level for each of the one or more commands in the queue.