Tri-Modal Carrier for a Semiconductive Wafer

• US 20150129121A1
• Filed: 11/11/2014
• Published: 05/14/2015
• Est. Priority Date: 11/11/2013
• Status: Active Grant

• Current Assignee: Diablo Capital, Inc.
• Original Assignee: Diablo Capital, Inc.
• Inventors: Smith, Eryn
• Granted Patent: US 9,754,809 B2
• Time in Patent Office: Days
• US Class Current: 156/247
• CPC Class Codes: H01L 21/6833 Details of electrostatic chucks
• CPC Class Codes: H02N 13/00 Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect

Abstract

A tri-modal carrier provides a structural platform to temporarily bond a semiconductive wafer and can be used to transport the semiconductive wafer or be used to perform manufacturing processes on the semiconductive wafer. The tri-modal carrier includes a doped semiconductive substrate, a plurality of electrostatic field generating (EFG) circuits, and a capacitance charging interface. A positive pole and a negative pole from each EFG circuit are embedded into the doped semiconductive substrate. An exposed portion of the doped semiconductive substrate is located between the positive pole and the negative pole, which is used as a biased pole for each EFG circuit. The combination of these poles for each EFG circuit is used to generate a non-uniform electrostatic field for bonding the semiconductive wafer. The tri-modal carrier also uses flat surface properties and the removal of trapped gas particles to strengthen the bond between the tri-modal carrier and the semiconductive wafer.

Claims

1. A tri-modal carrier for a semiconductive wafer comprises:

a doped semiconductive substrate;

a plurality of electrostatic field generating (EFG) circuits;

a capacitance charging interface;

said semiconductive substrate comprises a first face and a second face;

each of said plurality of EFG circuits comprises a positive pole, a negative pole, and a biased pole;

said plurality of EFG circuits being distributed across said doped semiconductive substrate;

said positive pole and said negative pole being embedded into said doped semiconductive substrate from said first face;

said positive pole and said negative pole being offset from each other across said first face;

an exposed portion of said doped semiconductive substrate being located between said positive pole and said negative pole for each of said plurality of EFG circuits;

said biased pole being said exposed portion of said doped semiconductive substrate; and

said capacitance charging interface being electrically connected to said positive pole, said negative pole, and said biased pole.

2. The tri-modal carrier for a semiconductive wafer as claimed in claim 1 comprises:

said capacitance charging interface comprises at least one positive terminal;

said at least one positive terminal being electrically connected to said positive poles of said plurality of EFG circuits; and

said at least one positive terminal being mounted onto said second face.

3. The tri-modal carrier for a semiconductive wafer as claimed in claim 1 comprises:

said capacitance charging interface comprises at least one negative terminal;

said at least one negative terminal being electrically connected to said negative poles from said plurality of EFG circuits; and

said at least one negative terminal being mounted onto said second face.

4. The tri-modal carrier for a semiconductive wafer as claimed in claim 1 comprises:

said capacitance charging interface comprises at least one biasing terminal;

said at least one biasing terminal being electrically connected to said biased poles from said plurality of EFG circuits; and

said at least one biasing terminal being mounted onto said second face.

5. The tri-modal carrier for a semiconductive wafer as claimed in claim 1 comprises:

said positive pole and said negative pole being flush with said exposed portions of said doped semiconductor substrate; and

a planarized surface being formed by said positive poles and said negative poles of said plurality of EFG circuits and said exposed portions of said doped semiconductor substrate.

6. The tri-modal carrier for a semiconductive wafer as claimed in claim 5 comprises:

a polishing film; and

said polishing film being superimposed upon said planarized surface.

7. The tri-modal carrier for a semiconductive wafer as claimed in claim 1 comprises:

an insulative film; and

said insulative film being positioned between said positive pole and said doped semiconductive substrate.

8. The tri-modal carrier for a semiconductive wafer as claimed in claim 1 comprises:

an insulative film; and

said insulative film being positioned between said negative pole and said doped semiconductive substrate.

9. The tri-modal carrier for a semiconductive wafer as claimed in claim 1, where said doped semiconductive substrate is made of a p-type semiconductor material.

10. The tri-modal carrier for a semiconductive wafer as claimed in claim 1, where said doped semiconductive substrate is made of an n-type semiconductor material.

11. A method of bonding and de-bonding a semiconductive wafer to the tri-modal carrier as claimed in claim 1 comprises the steps of:

placing said semiconductive wafer onto a planarized surface of said doped semiconductive substrate, wherein said planarized surface is formed by said positive poles and said negative poles of said plurality of EFG circuits and said exposed portions of said doped semiconductor substrate;

adhering said semiconductive wafer onto said doped semiconductive substrate by charging each of said plurality of EFG circuits through said capacitance charging interface;

adhering said semiconductive wafer onto said doped semiconductive substrate through intermolecular bonding between a flat surface of said semiconductive wafer and said planarized surface of said doped semiconductive substrate;

adhering said semiconductive wafer onto said doped semiconductive substrate by removing trapped gas particles between said semiconductive wafer and said doped semiconductive substrate; and

releasing said semiconductive wafer from said doped semiconductive substrate by discharging each of said plurality of EFG circuits through said capacitance charging interface.

12. The method of bonding and de-bonding a semiconductive wafer to the tri-modal carrier as claimed in claim 9 comprises the steps of:

positively charging said positive pole for each of said plurality of EFG circuits through an at least one positive terminal of said capacitance charging interface;

negatively charging said negative pole through said negative terminal of said capacitance charging interface; and

producing an electrostatic field between said positive pole and said negative pole for each of said plurality of EFG circuits, wherein said electrostatic field bonds to compositional impurities within said semiconductive wafer.

13. The method of bonding and de-bonding a semiconductive wafer to the tri-modal carrier as claimed in claim 9 comprises the steps of:

positively or negatively charging said biased pole for each of said plurality of EFG circuits through an at least one biasing terminal of said capacitance charging interface; and

producing an enrichment or depletion zone within said semiconductive wafer in order to adjust a dielectric constant of said enrichment or depletion zone, wherein said enrichment or depletion zone is located adjacent to said biased pole and is located in between said positive pole and said negative pole.

14. The method of bonding and de-bonding a semiconductive wafer to the tri-modal carrier as claimed in claim 9, wherein:

said positive pole and said negative pole being flush with said exposed portions of said doped semiconductor substrate; and

said positive poles, said negative poles, and said exposed portions for said plurality of EFG circuits forming said planarized surface.

15. The method of bonding and de-bonding a semiconductive wafer to the tri-modal carrier as claimed in claim 14 comprises the steps of:

wherein a polishing film being superimposed upon said planarized surface; and

adhering said semiconductive wafer onto said doped semiconductive substrate through intermolecular bonding between said flat surface of said semiconductive wafer and said polishing film of said doped semiconductive substrate.

16. The method of bonding and de-bonding a semiconductive wafer to the tri-modal carrier for claimed in claim 9 comprises:

placing said semiconductive wafer and said doped semiconductive substrate within a vacuum chamber; and

activating said vacuum chamber in order to remove said trapped gas particles between said semiconductive wafer and said doped semiconductive substrate.