SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

• US 20150129865A1
• Filed: 03/04/2013
• Published: 05/14/2015
• Est. Priority Date: 03/12/2012
• Status: Abandoned Application

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Miyamoto, Tadayoshi, Ito, Kazuatsu, Miyamoto, Mitsunobu, Takamaru, Yutaka
• Application Number:
  US14/384,468
• Publication Number:
  US 20150129865A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/134381 Hybrid switching mode, i.e. for applying an electric field with components parallel and orthogonal to the substrates
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/0271 comprising organic layers
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

This semiconductor device (100A) includes: a gate electrode (3); a gate insulating layer (4); an oxide layer (50) which is formed over the gate insulating layer (4) and which includes a semiconductor region (51) and a first conductor region (55) that contacts with the semiconductor region (51) and where the semiconductor region (51) at least partially overlaps with the gate electrode (3) with the gate insulating layer (4) interposed between them; a protective layer (8b) covering the upper surface of the semiconductor region (51); source and drain electrodes (6s, 6d) electrically connected to the semiconductor region (51); and a transparent electrode (9) arranged so as to overlap at least partially with the first conductor region (55) with a dielectric layer interposed between them. The drain electrode (6d) contacts with the first conductor region (55). When viewed along a normal to the substrate, an end portion of the protective layer (8b) is substantially aligned with an end portion of the drain, source or gate electrode (6d, 6s, 3), and at least a portion of a boundary between the semiconductor region (51) and the first conductor region (55) is substantially aligned with the end portion of the protective layer (8b).

Claims

1-18. -18. (canceled)

19. A semiconductor device comprising:

a substrate;

a gate electrode formed on the substrate;

a gate insulating layer formed over the gate electrode;

an oxide layer which is formed on the gate insulating layer and which includes a semiconductor region and a first conductor region that contacts with the semiconductor region and where the semiconductor region at least partially overlaps with the gate electrode with the gate insulating layer interposed between them;

a protective layer covering the upper surface of the semiconductor region;

source and drain electrodes electrically connected to the semiconductor region; and

a transparent electrode arranged so as to overlap at least partially with the first conductor region with a dielectric layer interposed between them,

wherein the drain electrode contacts with the first conductor region, and

when viewed along a normal to the substrate, an end portion of the protective layer is substantially aligned with an end portion of the drain electrode, an end portion of the source electrode or an end portion of the gate electrode, and at least a portion of a boundary between the semiconductor region and the first conductor region is substantially aligned with the end portion of the protective layer.

20. The semiconductor device of claim 19, wherein when viewed along a normal to the substrate, the semiconductor region is arranged inside of a profile of the gate electrode.

21. The semiconductor device of claim 19, wherein the oxide layer further includes a second conductor region located on the other side of the semiconductor region opposite from the first conductor region,

the drain electrode contacts with an upper surface of the first conductor region of the oxide layer and the source electrode contacts with an upper surface of the second conductor region of the oxide layer,

the transparent electrode is an upper transparent electrode arranged over the oxide layer with the dielectric layer interposed between them, and

when viewed along a normal to the substrate, the end portion of the protective layer is substantially aligned with the end portion of the gate electrode, and at least a portion of boundaries between the semiconductor region and the first and second conductor regions is substantially aligned with the end portion of the protective layer.

22. The semiconductor device of claim 19, wherein when viewed along a normal to the substrate, the semiconductor region is arranged inside of a profile of a region which overlaps with at least one of the gate, source and drain electrodes.

23. The semiconductor device of claim 19, wherein the source and drain electrodes are formed between the gate insulating layer and the oxide layer,

the semiconductor region of the oxide layer contacts with respective upper surfaces of the source and drain electrodes, and

when viewed along a normal to the substrate, at least a portion of the boundary between the semiconductor region and the first conductor region is substantially aligned with the end portion of the drain electrode.

24. The semiconductor device of claim 23, wherein the transparent electrode is an upper transparent electrode arranged over the oxide layer with the dielectric layer interposed between them.

25. The semiconductor device of claim 22, wherein the transparent electrode is a lower transparent electrode arranged between the oxide layer and the substrate and the dielectric layer includes at least a portion of the gate insulating layer.

26. The semiconductor device of claim 21, further comprising a source-drain connecting portion, the source-drain connecting portion includes:

a gate connecting layer formed out of the same conductive film as the gate electrode;

a source connecting layer formed out of the same conductive film as the source electrode; and

a transparent connecting layer formed out of the same transparent conductive film as the upper transparent electrode,

wherein the source connecting layer and the gate connecting layer are electrically connected together via the transparent connecting layer.

27. The semiconductor device of claim 25, further comprising a source-drain connecting portion, the source-drain connecting portion includes:

a gate connecting layer formed out of the same conductive film as the gate electrode; and

a source connecting layer formed out of the same conductive film as the source electrode,

wherein the source connecting layer contacts with the gate connecting layer inside a hole formed in the gate insulating layer.

28. The semiconductor device of claim 19, wherein the oxide layer includes In, Ga and Zn.

37. The semiconductor device of claim 23, wherein the transparent electrode is a lower transparent electrode arranged between the oxide layer and the substrate and the dielectric layer includes at least a portion of the gate insulating layer.

38. The semiconductor device of claim 24, further comprising a source-drain connecting portion, the source-drain connecting portion includes:

a gate connecting layer formed out of the same conductive film as the gate electrode;

a source connecting layer formed out of the same conductive film as the source electrode; and

a transparent connecting layer formed out of the same transparent conductive film as the upper transparent electrode,

wherein the source connecting layer and the gate connecting layer are electrically connected together via the transparent connecting layer.

29. A method for fabricating a semiconductor device, the method comprising the steps of:

(A) providing a substrate having a gate electrode and a gate insulating layer formed thereon;

(B) forming an oxide semiconductor layer over the gate insulating layer;

(C) forming a resistance-lowering-processing mask on the oxide semiconductor layer so as to cover a portion of the oxide semiconductor layer, the portion being located over the gate electrode, the step (C) including the steps of;

(C1) forming a resist film on the oxide semiconductor layer, and

(C2) exposing the resist film to radiation from an opposite side of the surface of the substrate using the gate electrode as a mask, thereby forming a resist layer; and

(D) lowering the resistance of a portion of the oxide semiconductor layer which is not covered with the resistance-lowering-processing mask to define a first conductor region, and turning the rest of the oxide semiconductor layer which has not had its resistance lowered into a semiconductor region, thereby forming an oxide layer including the semiconductor region and the first conductor region.

30. The method of claim 29, further comprising the steps of:

(E) forming source and drain electrodes so that the source and drain electrodes contact with an upper surface of the oxide layer; and

(F) forming a dielectric layer over the oxide layer and then forming an upper transparent electrode so that the upper transparent electrode overlaps with at least a portion of the first conductor region with the dielectric layer interposed between them.

31. The method of claim 29, wherein the step (C) includes the step of forming a protective film on the oxide semiconductor layer before the step (C1),

the step (C2) includes forming the resist layer on the protective film, and

the step (C) further includes the step of patterning the protective film using the resist layer as a mask, thereby forming a protective layer as the resistance-lowering-processing mask, after the step (C2).

36. The method of claim 29, wherein the oxide semiconductor layer includes In, Ga and Zn.

32. A method for fabricating a semiconductor device, the method comprising the steps of:

(a) providing a substrate having a gate electrode and a gate insulating layer formed thereon;

(b) forming source and drain electrodes on the gate insulating layer;

(c) forming an oxide semiconductor layer covering the source and drain electrodes;

(d) forming a resistance-lowering-processing mask on the oxide semiconductor layer so as to cover at least a portion of the oxide semiconductor layer, the portion being located over the gate electrode, the step (d) including the steps of;

(d1) forming a resist film on the oxide semiconductor layer, and

(d2) exposing the resist film to radiation from an opposite side of the surface of the substrate using the gate electrode as a mask, thereby forming a resist layer; and

(e) lowering the resistance of a portion of the oxide semiconductor layer which is not covered with the resistance-lowering-processing mask to define a first conductor region, and turning the rest of the oxide semiconductor layer which has not had its resistance lowered into a semiconductor region, thereby forming an oxide layer including the semiconductor region and the first conductor region.

33. The method of claim 32, further comprising the step (f) of forming a dielectric layer so that the dielectric layer contacts with an upper surface of the oxide layer and then forming an upper transparent electrode so that the upper transparent electrode overlaps with at least a portion of the first conductor region with the dielectric layer interposed between them.

34. The method of claim 32, further comprising the step of forming a lower transparent electrode on the substrate before the step (b),

wherein in the step (e), the first conductor region is arranged so as to overlap with the lower transparent electrode with at least a portion of the gate insulating layer interposed between them.

35. The method of claim 32, wherein the step (d) includes forming a protective film on the oxide semiconductor layer before the step (d1),

the step (d2) includes forming the resist layer on the protective film, and

the method further includes the step of patterning the protective film using the resist layer as a mask to form a protective layer as the resistance-lowering-processing mask after the step (d2).