ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE

• US 20150129882A1
• Filed: 12/19/2013
• Published: 05/14/2015
• Est. Priority Date: 07/23/2013
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Inventors: Jiang, Qinghua, Li, Xiaohe, Liu, Yong, Shao, Xianjie, Li, Hongmin
• Granted Patent: US 9,219,082 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785

Abstract

The invention relates to an array substrate for a display device and to a method for manufacturing an array substrate comprising a thin-film transistor (“TFT”). An array substrate according to an embodiment of the invention comprises a source electrode, a gate electrode and a drain electrode, wherein the gate electrode is located on a first metal layer, the source electrode and the drain electrode are located on a second metal layer, and in the case that dislocation occurs between the first metal layer and the second metal layer, the area of the overlapping region between the source electrode and the gate electrode keeps constant.

Claims

1. An array substrate comprising a thin film transistor, the thin film transistor comprises a source electrode, a gate electrode and a drain electrode, wherein the gate electrode is located on a first metal layer, and the source electrode and the drain electrode are located on a second metal layer, wherein:

the shapes of the source electrode and the gate electrode meet the condition that, in the case that dislocation occurs between the first metal layer and the second metal layer, the area of the overlapping region between the source electrode and the gate electrode keeps constant.

2. The array substrate according to claim 1, wherein the source electrode comprises an overlapping region with the gate electrode, and a first part region and a second part region located on the two sides of the gate electrode respectively in a direction parallel to the gate line;

in the case that dislocation occurs between the first metal layer and the second metal layer, an increased/decreased bottom area of the first part region equals to a decreased/increased bottom area of the second part region.

3. The array substrate according to claim 2, wherein a pattern consisted of the first part region, the second part region and the overlapping region with the gate electrode comprises a U-shaped pattern with an opening facing a direction parallel to the gate line and an L-shaped pattern coupled with the closed side of the U-shaped pattern and arranged laterally;

wherein the first part region is located at a position on one side edge of the U-shaped pattern that extends out of the gate electrode or located at a position on the two side edges of the U-shaped pattern that extend out of the gate electrode, and the second part region is located at a position on the L-shaped pattern that extends out of the gate electrode.

4. The array substrate according to claim 2, wherein a pattern consisted of the first part region, the second part region and the overlapping region between the source electrode and the gate electrode is an analogous ±

-shaped pattern;

wherein the first part region is located at a position on the first side and/or the second side of the ±

-shaped pattern that extends out of the gate electrode in a first direction parallel to the gate line; and

the second part region is located at a position on the first side and/or the second side of the ±

-shaped pattern that extends out of the gate electrode in a second direction opposite to the first direction, wherein the first side and the second side are parallel with each other.

5. The array substrate according to claim 2, further comprising a data line coupled with the drain electrode, wherein the minimum distance from the first part region and the second part region to the data line is no less than a given threshold that is in the range of 5 μ

m to 10 μ

m.

6. The array substrate according to claim 3, further comprising a data line coupled with the drain electrode, wherein the minimum distance from the first part region and the second part region to the data line is no less than a given threshold that is in the range of 5 μ

m to 10 μ

m.

7. The array substrate according to claim 4, further comprising a data line coupled with the drain electrode, wherein the minimum distance from the first part region and the second part region to the data line is no less than a given threshold that is in the range of 5 μ

m to 10 μ

m.

8. The array substrate according to claim 1, wherein the gate electrode comprises a first part region and a second part region that are separated from each other, and the source electrode comprises a third part region that overlaps with the first part region and a fourth part region that overlaps with the second part region;

in the case that dislocation occurs between the first metal layer and the second metal layer, an increased/decreased bottom area of the third part region equals to a decreased/increased bottom area of the fourth part region.

9. The array substrate according to claim 8, wherein the pattern of the source electrode is an analogous inversed T-shaped pattern consisted of the third part region, the fourth part region and the area between the first part region and the second part region;

wherein the third part region is located at a position on the inversed T-shaped pattern that overlaps with the first part region in a first direction parallel to the gate line, and the fourth part region is located at a position on the inversed T-shaped pattern that overlaps with the second part region in a second direction opposite to the first direction.

10. A display device, comprising the array substrate according to claim 1.

11. A method for manufacturing the array substrate according to claim 1, comprising:

forming a gate electrode on a substrate, wherein the gate electrode is located on a first metal layer;

forming a gate electrode insulating layer, which covers the gate electrode, on the substrate; and

forming an active layer, and a source electrode and a drain electrode located on the active layer in turn on the gate electrode insulating layer, wherein the source electrode and the drain electrode are located on a second metal layer;

wherein in the case that dislocation occurs between the first metal layer and the second metal layer, the area of the overlapping region between the source electrode and the gate electrode keeps constant.