SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

• US 20150130041A1
• Filed: 11/06/2014
• Published: 05/14/2015
• Est. Priority Date: 11/08/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Heeseok Lee, Jong-Won Lee
• Inventors: LEE, Heeseok, LEE, Jong-won, SEO, Jangmee
• Granted Patent: US 9,324,657 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1082 for improving alignment between containers, e.g. interlocking features
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

Provided are semiconductor packages and methods of fabricating the same. The method may include, stacking a lower semiconductor chip on a lower package substrate, forming a lower molding layer on the lower package substrate, forming a connecting through-hole and an element through-hole by performing a laser drilling process on the lower molding layer, and stacking an upper package substrate having a bottom surface to which a passive element is bonded on the lower package substrate to insert the passive element into the element through-hole.

Claims

1. A method of fabricating a semiconductor package, the method comprising:

stacking a lower semiconductor chip on a lower package substrate;

forming a lower molding layer on the lower package substrate;

forming a connecting through-hole and an element through-hole by performing a laser drilling process on the lower molding layer; and

stacking an upper package substrate having a bottom surface to which a passive element is bonded on the lower package substrate to insert the passive element into the element through-hole.

2. The method of claim 1, wherein the element through-hole is formed between the lower semiconductor chip and the connecting through-hole.

3. The method of claim 2, wherein the element through-hole includes a plurality of element through-holes, and the passive element includes a plurality of passive elements provided in the plurality of element through-holes, and

wherein the plurality of element through-holes are disposed at both sides of the lower semiconductor chip.

4. The method of claim 2, wherein the element through-hole is disposed at one side of the lower semiconductor chip.

5. The method of claim 1, wherein the connecting through-hole is formed to expose a lower conductive connection part formed on the lower package substrate, and

wherein a bottom surface of the element through-hole is higher than a top surface of the lower package substrate.

6. The method of claim 1, wherein the connecting through-hole is formed to expose a lower conductive connection part formed on the lower package substrate, and

wherein the element through-hole is formed to expose a top surface of the lower package substrate.

7. A semiconductor package comprising:

a lower package including a lower package substrate, a lower semiconductor chip stacked on the lower package substrate, and a lower molding layer covering the lower semiconductor chip on the lower package substrate and including an element through-hole; and

an upper package stacked on the lower package, the upper package including an upper package substrate, an upper semiconductor chip stacked on the upper package substrate, and a passive element bonded to a bottom surface of the upper package substrate,

wherein the passive element is inserted in the element through-hole.

8. The semiconductor package of claim 7, wherein the lower molding layer further includes a connecting through-hole in which a conductive connection part is inserted,

wherein the conductive connection part electrically connects the lower package substrate to the upper package substrate, and

wherein the element through-hole is disposed between the lower semiconductor chip and the connecting through-hole.

9. The semiconductor package of claim 8, wherein the element through-hole includes a plurality of element through-holes, and the passive element includes a plurality of passive elements inserted in the plurality of element through-holes, and

wherein the plurality of element through-holes are disposed at both sides of the lower semiconductor chip.

10. The semiconductor package of claim 8, wherein the connecting through-holes includes a plurality of connecting through-holes, and the conductive connection part includes a plurality of conductive connection parts inserted in the plurality of connecting through-holes,

wherein the element through-hole is disposed between a first sidewall of the lower semiconductor chip and the conductive connection part adjacent to the first sidewall of the lower semiconductor chip, and

wherein a distance between the first sidewall of the lower semiconductor chip and the conductive connection part adjacent to the first sidewall of the lower semiconductor chip is greater than a distance between a second sidewall of the lower semiconductor chip and the conductive connection part adjacent to the second sidewall of the lower semiconductor chip.

11. The semiconductor package of claim 7, wherein a bottom surface of the element through-hole is higher than a top surface of the lower package substrate.

12. The semiconductor package of claim 11, further comprising:

a first element interconnection and a second element interconnection provided on the bottom surface of the upper package substrate,

wherein the first element interconnection and the second element interconnection are electrically connected to the passive element.

13. The semiconductor package of claim 7, wherein the element through-hole exposes a top surface of the lower package substrate.

14. The semiconductor package of claim 13, further comprising:

a first element interconnection disposed on the top surface of the lower package substrate and exposed by the element through-hole; and

a second element interconnection disposed on the bottom surface of the upper package substrate and facing the first element interconnection,

wherein one surface of the passive element is in contact with the first element interconnection, and another surface of the passive element is in contact with the second element interconnection.

15. The semiconductor package of claim 8, wherein the conductive connection part is in contact with an inner sidewall of the connecting through-hole.

16. A semiconductor package comprising:

a lower package substrate;

a lower semiconductor chip mounted on the lower package substrate;

an upper package substrate stacked on the lower package substrate;

at least one upper semiconductor chip mounted on the upper package substrate; and

a passive element disposed on a bottom surface of the upper package substrate.

17. The semiconductor package of claim 16, wherein the lower package substrate includes a lower molding layer in which a connecting through-hole and an element through-hole are formed,

wherein the passive element is inserted in the element through-hole, and

wherein a conductive connection part which electrically connects the lower package substrate to the upper package substrate is inserted in the connecting through-hole.

18. The semiconductor package of claim 17, wherein the element through-hole includes a plurality of element through-holes, and the passive element includes a plurality of passive elements inserted in the plurality of element through-holes, and

wherein the connecting through-holes includes a plurality of connecting through-holes, and the conductive connection part includes a plurality of conductive connection parts inserted in the plurality of connecting through-holes.

19. The semiconductor package of claim 17, wherein a bottom surface of the element through-hole is higher than a top surface of the lower package substrate.

20. The semiconductor package of claim 17, wherein the element through-hole exposes a top surface of the lower package substrate.