Semiconductor Package Comprising Two Semiconductor Modules and Laterally Extending Connectors

• US 20150130048A1
• Filed: 11/12/2013
• Published: 05/14/2015
• Est. Priority Date: 11/12/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hohlfeld, Olaf, Hoegerl, Juergen, Beer, Gottfried, Hoier, Magdalena
• Granted Patent: US 9,196,510 B2
• Time in Patent Office: Days
• US Class Current: 257/735
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/10272 Silicon Carbide [SiC]
• CPC Class Codes: H01L 2924/1033 Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/1203 Rectifying Diode
• CPC Class Codes: H01L 2924/12043 Photo diode
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor package includes a mold body having a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, a first semiconductor module including a plurality of first semiconductor chips and a first encapsulation layer disposed above the first semiconductor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of second semiconductor channels and a second encapsulation layer disposed above the second semiconductor channels. The semiconductor package further includes a plurality of external connectors extending through one or more of the side faces of the mold body.

Claims

1. A semiconductor package, comprising:

a mold body comprising a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces;

a first semiconductor module comprising a plurality of first semiconductor chips and a first encapsulation layer disposed above the first semiconductor chips;

a second semiconductor module disposed above the first semiconductor module, the second semiconductor module comprising at least one second semiconductor chip and a second encapsulation layer disposed above the at least one second semiconductor chip; and

a plurality of external connectors extending through one or more of the side faces of the mold body.

2. The semiconductor package according to claim 1, wherein

a first group of the external connectors is electrically connected to the first semiconductor module, and a second group of the external connectors is electrically connected to the second semiconductor module.

3. The semiconductor package according to claim 1, wherein

the external connectors are mechanically connected to the second semiconductor module.

4. The semiconductor package according to claim 1, wherein

the second semiconductor module comprises a printed circuit board and the at least one second semiconductor chip is connected to the printed circuit board.

5. The semiconductor package according to claim 4, wherein

the external connectors are mechanically connected to the printed circuit board.

6. The semiconductor package according to claim 4, wherein

the printed circuit board comprises through-connections and a group of the external connectors is connected to the through-connections.

7. The semiconductor package according to claim 1, wherein

each one of the external connectors comprises a first portion disposed mainly within the mold body, and a second portion disposed outside of the mold body, and wherein the second portion is bent at a right angle with respect to the first portions.

8. The semiconductor package according to claim 7, wherein

the first portions of the external connectors lie in one and the same plane.

9. The semiconductor package according to claim 7, wherein

the second portions of the external connectors comprise one or more of equal direction and equal length.

10. The semiconductor package according to claim 1, wherein

the mold body comprises two vertical through-holes formed in two opposing side edges of the mold body, each one of the through-holes extending from the first main face of the mold body to the second main face of the mold body.

11. The semiconductor package according to claim 1, wherein

the first semiconductor chips comprise semiconductor transistor chips and the at least one second semiconductor chip comprises a plurality of semiconductor driver channels.

12. The semiconductor package according to claim 11, wherein

the semiconductor transistor chips are connected to form an AC/AC converter circuit, an AC/DC converter circuit, a DC/AC converter circuit, a frequency converter, or a DC/DC converter circuit.

13. A semiconductor package, comprising:

a mold body comprising a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces;

a semiconductor power module comprising a plurality of semiconductor power transistor chips;

a semiconductor driver module comprising a plurality of semiconductor driver channels, the semiconductor driver module being disposed above and attached to the semiconductor power module; and

a plurality of external connectors extending through one or more side faces of the mold body.

14. The semiconductor package according to claim 13, wherein

the mold body comprises four side faces and the external connectors extend through all four side faces of the mold body.

15. The semiconductor package according to claim 13, wherein

the semiconductor power module comprises a first encapsulation layer disposed above the semiconductor power transistor chips, and wherein the semiconductor power module comprises a plurality of sub-modules separated from each other by the first encapsulation layer.

16. The semiconductor package according to claim 15, further comprising:

a redistribution layer disposed above the first encapsulation layer, the redistribution layer comprising metallic layers connecting selected ones of the semiconductor power transistor chips.

17. The semiconductor package according to claim 13, wherein

each one of the semiconductor power transistor chips is connected to one or two semiconductor driver chips.

18. A method for fabricating a semiconductor package, the method comprising:

providing a first semiconductor module, the first semiconductor module comprising a plurality of semiconductor transistor chips and a first encapsulation layer disposed above the semiconductor transistor chips;

arranging a plurality of semiconductor driver channels above the first semiconductor module and connecting the semiconductor driver channels with the semiconductor transistor chips;

arranging a plurality of laterally extending external connectors; and

applying a second encapsulation layer to the semiconductor driver channels and to the external connectors.

19. The method according to claim 18, further comprising:

providing a printed circuit board;

connecting the semiconductor driver channels to the printed circuit board;

arranging the printed circuit board at a distance to the first semiconductor module;

connecting the external connectors to the printed circuit board; and

applying the second encapsulation layer after connecting the external connectors to the printed circuit board.

20. The method according to claim 18, further comprising:

applying the second encapsulation layer by transfer molding.