Transistor and Tunable Inductance

• US 20150130556A1
• Filed: 11/14/2013
• Published: 05/14/2015
• Est. Priority Date: 11/14/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Bakalski, Winfried
• Granted Patent: US 9,275,986 B2
• Time in Patent Office: Days
• US Class Current: 333/103
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

According to a first aspect embodiments provide a transistor including at least one gate region between at least one drain region and at least one source region, wherein a ratio between a width of the gate region and a length of the gate region exceeds 300.

Claims

1. A transistor, comprising:

at least one gate region between at least one drain region and at least one source region, wherein a ratio between a width of the gate region and a length of the gate region exceeds 300.

2. The transistor of claim 1, wherein the length of the gate region corresponds to a length of a conduction channel between the drain region and the source region.

3. The transistor of claim 1, further comprising

a stack of at least one semiconductor layer and a plurality of metal layers,

wherein the at least one drain region and the at least one source region are formed in the at least one semiconductor layer, and

wherein a plurality of interconnected drain contact regions and a plurality of interconnected source contact regions are formed in the plurality of metal layers.

4. The transistor of claim 3, wherein the drain region is connected to a drain contact pad via an array of vertically stacked drain contact regions, wherein a first drain contact region is formed in a first metal layer and wherein a second drain contact region is formed in a second metal layer, and

wherein the source region is connected to a source contact pad via an array of vertically stacked source metal regions, wherein a first source metal region is formed in the first metal layer and wherein a second source metal region is formed in the second metal layer.

5. The transistor of claim 3, wherein the array of vertically stacked drain contact regions and the array of vertically stacked source contact regions are formed in the plurality of metal layers to yield an off-mode capacitance of the transistor above a predefined threshold.

6. The transistor of claim 5, wherein the off-mode capacitance of the transistor at a reference frequency f_ref is

7. The transistor of claim 3, wherein a maximum distance between a drain contact region and a source contact region of a same metal layer is smaller than or equal to a maximum distance between the drain region and the source region.

8. The transistor of claim 3, wherein a minimum distance between a drain contact region and a source contact region in a same metal layer corresponds to the length of the gate region.

9. The transistor of claim 3, wherein a length of a drain contact region substantially corresponds to the width of the at least one gate region and/or wherein a length of a source contact region substantially corresponds to the width of the at least one gate region.

10. The transistor of claim 3, wherein a first drain contact region and an adjacent second drain contact region are connected via a Metal-Insulator-Metal capacitor and/or wherein a first source contact region and an adjacent second source contact region are connected via a Metal-Insulator-Metal capacitor.

11. The transistor of claim 1, wherein the at least one gate region, the at least one drain region, and/or the at least one source region are dimensioned in a volume of the transistor such that an inductance of the transistor deviates from

12. The transistor of claim 1, wherein the transistor comprises a multi-finger MOS transistor structure and wherein the gate region corresponds to one of a plurality of gate fingers of the multi-finger MOS transistor structure.

13. The transistor of claim 1, wherein an area of the transistor has a rectangular shape, and wherein a number of gate fingers associated with a breadth of the area is less than 30.

14. The transistor of claim 1, wherein the transistor is formed in a stack of at least one semiconductor layer for the drain regions and the source regions and at least one metal layer for related contact regions, wherein a shape of metal contact regions in the at least one metal layer is formed to model a shape of a slab inductor.

15. A transistor, comprising:

a stack of at least one semiconductor layer and a plurality of metal layers;

at least one drain region and at least one source region formed in the at least one semiconductor layer; and

a stack of interconnected drain metal regions formed in the plurality of metal layers, wherein the plurality of interconnected drain metal regions is electrically connected to the drain region;

a stack of interconnected source metal regions formed in the plurality of metal layers, wherein the plurality of interconnected source metal regions is electrically connected to the source region;

wherein a maximum distance between a drain metal region and a source metal region of a same metal layer is smaller than or equal to a maximum distance between the drain region and the source region.

16. The transistor of claim 15, wherein the drain region is connected to a drain contact pad via the stack of drain metal regions, wherein the stack of drain metal regions is arranged as an array of vertically stacked drain metal regions, wherein a first drain metal region is formed in a first metal layer and wherein a second drain metal region is formed above the first drain metal region in a vertically adjacent second metal layer, and

wherein the source region is connected to a source contact pad via the stack of source metal regions, wherein the stack of source metal regions is arranged as an array of vertically stacked source metal regions, wherein a first source metal region is formed in the first metal layer and wherein a second source metal region is formed above the first source metal region in the second metal layer.

17. The transistor of claim 15, wherein the stack of interconnected drain metal regions and the stack of interconnected source metal regions are formed in the plurality of metal layers to yield an off-mode capacitance C_off of the transistor above a predefined threshold, wherein the off-mode capacitance C_off of the transistor at a reference frequency f_ref is

18. The transistor of claim 15, wherein a first drain metal region and an adjacent second drain metal region are connected via a Metal-Insulator-Metal capacitor and/or wherein a first source metal region and an adjacent second source metal region are connected via a Metal-Insulator-Metal capacitor.

19. The transistor of claim 15, comprising at least one gate region between the at least one drain region and the at least one source region, wherein a ratio between a width of the gate region and a length of the gate region exceeds 300.

20. A tunable inductance comprising a plurality of multi-finger field effect transistors, each multi-finger field effect transistor comprising multiple fingers, wherein a ratio between a width of a finger and a length of the finger exceeds 300, and wherein an inductance of a multi-finger field effect transistor depends on a dimension of a metallization associated with its multiple fingers.

21. The tunable inductance of claim 21, further comprising control circuitry to decrease the tunable inductance by switching one or more multi-finger field effect transistors in an off-mode, and to increase the tunable inductance by switching one or more multi-finger field effect transistors in an on-mode.