DATA PROCESSING DEVICE AND MANUFACTURING METHOD THEREOF

• US 20150131356A1
• Filed: 11/05/2014
• Published: 05/14/2015
• Est. Priority Date: 11/08/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Granted Patent: US 9,385,054 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 2029/1802 Address decoder
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/18 Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
• CPC Class Codes: G11C 29/78 using programmable devices
• CPC Class Codes: G11C 29/785 with redundancy programming schemes
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A method by which a defective memory cell can be efficiently excluded from a memory cell array is provided. In one embodiment, the memory cell array includes M word lines and (N+K) bit lines. K of the bit lines are spares (i.e., redundant bit lines). Programmable switches in a switch array are programmed so that the switch array connects a driver that drives the bit lines to N bit lines that are not connected to defective memory cells. The memory cell array is tested by a test circuit connected to the bit lines in such a manner that the test circuit transmits and receives a signal to and from the bit lines via the switch array. The test circuit may be formed using a reconfigurable circuit. Other embodiments may be claimed.

Claims

1. A data processing device comprising:

a memory cell array comprising a first wiring; and

a switch array operationally connected to the memory cell array, the switch array comprising;

a plurality of first programmable switches; and

the first wiring,

wherein the switch array is capable of transmitting a test signal to the memory cell array in an operation for detecting a defective memory cell in the memory cell array, and

wherein the switch array is capable of preventing data transmission to the defective memory cell.

2. A data processing device according to claim 1,

wherein the memory cell array comprises:

a plurality of first wirings including the first wiring;

a plurality of second wirings; and

a plurality of memory cells at intersections between the plurality of first wirings and the plurality of second wirings,

wherein the switch array comprises;

the plurality of first wirings; and

a plurality of third wirings,

wherein the plurality of first programmable switches is at intersections between the plurality of first wirings and the plurality of third wirings, and

wherein the plurality of first programmable switches is each capable of electrically connecting one of the plurality of first wirings to one of the plurality of third wirings.

3. The data processing device according to claim 2, wherein the plurality of first wirings are bit lines and the plurality of second wirings are word lines.

4. The data processing device according to claim 2, wherein the number of the plurality of third wirings is larger than the number of the plurality of first wirings.

5. The data processing device according to claim 2, wherein at least one of the plurality of third wirings is not electrically connected to any of the plurality of first wirings.

6. The data processing device according to claim 2,

wherein the plurality of first programmable switches each comprises a first transistor and a second transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of the plurality of third wirings,

wherein the other of the source and the drain of the first transistor is electrically connected to one of the plurality of first wirings,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the second transistor comprises a channel formation region, and

wherein the channel formation region includes an oxide semiconductor.

7. The data processing device according to claim 2, further comprising:

a plurality of fourth wirings intersecting with the plurality of first wirings;

a plurality of second programmable switches at intersections between the plurality of fourth wirings and the plurality of first wirings, the plurality of second programmable switches each being capable of electrically connecting one of the plurality of fourth wirings to one of the plurality of first wirings; and

a driver circuit capable of supplying a signal to the plurality of fourth wirings.

8. The data processing device according to claim 7, wherein the driver circuit is a test circuit capable of transmitting and receiving the test signal.

9. The data processing device according to claim 7, wherein the driver circuit comprises at least one programmable logic circuit.

10. A data processing device comprising:

a plurality of first wirings;

a plurality of second wirings;

a plurality of third wirings;

a memory cell array comprising a plurality of memory cells at intersections between the plurality of first wirings and the plurality of third wirings;

a switch array comprising a plurality of first programmable switches at intersections between the plurality of second wirings and the plurality of third wirings, the plurality of first programmable switches each being capable of electrically connecting one of the plurality of second wirings to one of the plurality of third wirings;

a first driver circuit capable of supplying a signal to the plurality of first wirings; and

a second driver circuit capable of supplying a signal to the plurality of second wirings.

11. The data processing device according to claim 10, wherein the plurality of first wirings are word lines and the plurality of third wirings are bit lines.

12. The data processing device according to claim 10, wherein the number of the plurality of second wirings is larger than the number of the plurality of third wirings.

13. The data processing device according to claim 10, wherein at least one of the plurality of second wirings is not electrically connected to any of the plurality of third wirings.

14. The data processing device according to claim 10,

wherein the plurality of first programmable switches each comprises a first transistor and a second transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of the plurality of second wirings,

wherein the other of the source and the drain of the first transistor is electrically connected to one of the plurality of third wirings,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the second transistor comprises a channel formation region, and

wherein the channel formation region includes an oxide semiconductor.

15. The data processing device according to claim 10, further comprising:

a plurality of fourth wirings intersecting with the plurality of third wirings;

a plurality of second programmable switches at intersections between the plurality of fourth wirings and the plurality of third wirings, the plurality of second programmable switches each being capable of electrically connecting one of the plurality of fourth wirings to one of the plurality of third wirings; and

a third driver circuit capable of supplying a signal to the plurality of fourth wirings.

16. The data processing device according to claim 15, wherein the third driver circuit is a test circuit capable of transmitting and receiving a test signal.

17. The data processing device according to claim 15, wherein the third driver circuit comprises at least one programmable logic circuit.

18. A method for manufacturing the data processing device according to claim 10, comprising the steps of:

testing the plurality of memory cells; and

programming the plurality of first programmable switches when a defective memory cell is detected in the testing step so that one of the plurality of third wirings electrically connected to the defective memory cell is not electrically connected to any of the plurality of second wirings, and each one of the rest of the plurality of third wirings is electrically connected to each corresponding one of the plurality of second wirings.