Three Dimensional Nonvolatile Memory Cell Structure with Upper Body Connection
First Claim
Patent Images
1. A non-volatile memory device, comprising:
- a substrate comprising a source line region of a first conductivity type formed at a surface of the substrate; and
a NAND flash memory array formed over the substrate comprising a plurality of NAND flash strings, each comprising a vertical channel string body connected between the source line region and an upper semiconductor layer which extends parallel to the surface of the substrate, where the upper semiconductor layer comprises;
a horizontal string body region connected to each vertical channel string body,a drain region of the first conductivity type connected to each horizontal string body region, anda body line contact region of a second, opposite conductivity type connected to each horizontal string body region.
5 Assignments
0 Petitions
Accused Products
Abstract
A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines.
-
Citations
21 Claims
-
1. A non-volatile memory device, comprising:
-
a substrate comprising a source line region of a first conductivity type formed at a surface of the substrate; and a NAND flash memory array formed over the substrate comprising a plurality of NAND flash strings, each comprising a vertical channel string body connected between the source line region and an upper semiconductor layer which extends parallel to the surface of the substrate, where the upper semiconductor layer comprises; a horizontal string body region connected to each vertical channel string body, a drain region of the first conductivity type connected to each horizontal string body region, and a body line contact region of a second, opposite conductivity type connected to each horizontal string body region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A NAND Flash memory cell array formed on a substrate comprising a plurality of semiconductor string bodies running in a direction perpendicular to a surface of the substrate, where each semiconductor string body is connected between an n-type source region formed in the substrate and an upper semiconductor layer formed over the substrate, where each upper semiconductor layer comprises:
-
a horizontal string body region connected to and formed over an associated semiconductor string body, an n-type conductivity region connected through each horizontal string body region to the associated semiconductor string body, and a p-type conductivity region connected through each horizontal string body region to the associated semiconductor string body, where the n-type conductivity region and p-type conductivity region are each laterally offset from the associated semiconductor string body. - View Dependent Claims (13, 14, 15, 16, 17, 18)
-
-
19. A method for reading an addressed memory cell transistor from a plurality of NAND flash strings, each comprising a vertical channel string body in which a plurality of series-connected transistors are formed between a substrate source line region and an upper semiconductor layer, the plurality of series-connected transistors comprising an upper select gate transistor, a lower select gate transistor, and a plurality of memory cell transistors formed between the upper and lower select gate transistors, comprising:
-
applying a bit line read voltage to a bit line conductor which is connected through an n-type string drain region formed in the upper semiconductor layer to a selected flash string on which the addressed memory cell transistor is formed; applying a body voltage to a body line conductor which is connected through a p-type string region formed in the upper semiconductor layer to the selected flash string on which the addressed memory cell transistor is formed; and applying a read gate voltage to the addressed memory cell transistor while otherwise applying a positive gate voltage to the other series-connected transistors formed on the selected flash string, thereby reading a value from the addressed memory cell transistor that is transferred through the n-type string drain region formed in the upper semiconductor layer and to the bit line conductor under control of the upper select gate transistor for the selected flash string. - View Dependent Claims (20)
-
-
21. A method for erasing an erase block of NAND flash strings, each comprising a vertical channel string body in which a plurality of series-connected transistors are formed between a substrate source line region and an upper semiconductor layer, the plurality of series-connected transistors comprising an upper select gate transistor, a lower select gate transistor, and a plurality of memory cell transistors formed between the upper and lower select gate transistors, comprising:
-
applying a large positive erase voltage to a body line conductor which is connected through p-type string regions formed in the upper semiconductor layer to the erase block of NAND flash strings, thereby charging the vertical channel string bodies in the erase block of NAND flash strings; applying a smaller erase gate voltage to the plurality of series-connected transistors formed on the erase block of NAND flash strings; and floating the substrate source line and one or more bit line conductors which are connected through an n-type string drain regions formed in the upper semiconductor layer to the erase block of NAND flash strings.
-
Specification