HIGH CAPACITY MEMORY SYSTEM USING STANDARD CONTROLLER COMPONENT

• US 20150131388A1
• Filed: 11/11/2014
• Published: 05/14/2015
• Est. Priority Date: 11/11/2013
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Rajan, Suresh, Best, Scott C.
• Granted Patent: US 9,165,639 B2
• Time in Patent Office: Days
• US Class Current: 365/189.02
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

Claims

1. A memory module comprising:

a plurality of device sites; and

a data (DQ) buffer component coupled to the plurality of device sites, wherein the DQ buffer component is to operate in a first mode when the memory module is inserted onto a first type of memory channel with multi-drop data-links and to operate in a second mode when the memory module is inserted onto a second type of memory channel with point-to-point data-links.

2. The memory module of claim 1, wherein the DQ buffer component is programmed to operate as a repeater in the first mode and in the second mode.

3. The memory module of claim 1, wherein the DQ buffer component is programmed to operate as a repeater in the first mode and as a multiplexer in the second mode.

4. The memory module of claim 1, wherein the DQ buffer component comprises:

two primary ports to couple to two of the multi-drop data-links in the first mode and to couple to two of the point-to-point data-links in the second mode; and

two secondary ports coupled to two of the plurality of device sites.

5. The memory module of claim 4, wherein the DQ buffer component comprises:

a first bi-directional path between a first primary port of the two primary ports and a first secondary port of the two secondary ports;

a second bi-directional path between a second primary port of the two primary ports and a second secondary port of the two secondary ports;

a third bi-directional path between the first primary port and the second secondary port; and

a fourth bi-directional path between the second primary port and the first secondary port.

6. The memory module of claim 1, wherein the multi-drop data-links are shared with all other memory modules connected to a memory controller to which the memory module is connected, and wherein the point-to-point data-links do not connect to all of the other memory modules connected to the memory controller.

7. The memory module of claim 1, further comprising a plurality of dynamic random access memory (DRAM) devices disposed at the plurality of device sites, wherein the point-to-point data-links are at least one of point-to-point (P-to-P) links or point-to-two-points (P-to-2P) links.

8. The memory module of claim 1, further comprising

a command and address (CA) buffer component, comprising:

primary data-links to receive chip select (CS) information from a memory controller to select the memory module as a selected module for access, wherein other memory modules connected to the memory controller are unselected modules; and

secondary data-links to retransmit the CS information to at least one of the unselected modules.

9. The memory module of claim 1, further comprising

a command and address (CA) buffer component comprising:

primary data-links to receive chip select (CS) information from a memory controller when the memory module is selected by the memory controller; and

secondary data-links to receive a copy of the CS information retransmitted from another memory module connected to the memory controller when the memory module is not selected by the memory controller.

10. The memory module of claim 1, further comprising:

a plurality of dynamic random access memory (DRAM) devices disposed at the plurality of device sites; and

a plurality of data (DQ) buffer components coupled to the plurality of DRAM devices, wherein the plurality of DQ buffer components individually comprise;

three primary ports to couple to three of the multi-drop data-links in the first mode and to couple to three of the point-to-point data-links in the second mode; and

three secondary ports coupled to three of the plurality of DRAM devices.

11. The memory module of claim 10, further comprising a private bus coupled between at least two of the plurality of DQ buffer components.

12. The memory module of claim 1, further comprising

a command and address (CA) buffer component coupled to CA links and a private bus disposed a motherboard substrate, the CA buffer component to receive CS information from a memory controller over the CA links and to broadcast a copy of the CS information on the private bus.

13. The memory module of claim 12, wherein the CA buffer component shares the copy of the CS information on the private bus to other memory modules connected to the memory controller with approximately a one-clock-cycle delay.

14. The memory module of claim 1, wherein the DQ buffer component further comprises:

a first multiplexer comprising two inputs coupled to two primary ports and an output coupled to a second secondary port of two secondary ports;

a second multiplexer comprising two inputs coupled to the two primary ports and an output coupled to a first secondary port of the two secondary ports;

a third multiplexer comprising two inputs coupled to the two secondary ports and an output coupled to a first primary port of the two primary ports; and

a fourth multiplexer comprising two inputs coupled to the two secondary ports and an output coupled to a second primary port of the two primary ports.

15. The memory module of claim 14, wherein the DQ buffer component further comprises:

first synchronization logic coupled between the output of the first multiplexer and the second secondary port;

second synchronization logic coupled between the output of the second multiplexer and the first secondary port;

third synchronization logic coupled between the output of the third multiplexer and the first primary port; and

fourth synchronization logic coupled between the output of the fourth multiplexer and the second primary port.

16. The memory module of claim 15, wherein the DQ buffer component further comprises:

a first bypass path from the first primary port to a third input of the fourth multiplexer; and

a second bypass path from the second primary port to a third input of the third multiplexer.

17. The memory module of claim 15, wherein the DQ buffer component further comprises:

a fifth multiplexer comprising two inputs coupled to an output of the third synchronization logic and a first bypass path coupled the second primary port and an output coupled to the first primary port; and

a sixth multiplexer comprising two inputs coupled to an output of the fourth synchronization logic and a second bypass path coupled to the first primary port and an output coupled to the second primary port.

18. The memory module of claim 14, wherein the DQ buffer component further comprises a passive asynchronous bypass path directly coupled between the first primary port and the second primary port.

19. The memory module of claim 1, wherein at least one of the plurality of device sites comprises at least one of a single device, a two-package stack, at least a two-die stack, or a four-die stack with a micro-buffer component.

20. The memory module of claim 1, further comprising:

eighteen dynamic random access memory (DRAM) devices disposed at the plurality of device sites;

nine DQ buffer components coupled to the eighteen DRAM devices, each of the nine DQ buffer components being coupled to a pair of the eighteen DRAM devices, wherein the nine DQ buffer components includes the DQ buffer component; and

a command and address (CA) buffer component coupled to the eighteen DRAM devices.

21. A method comprising:

operating a memory module in a first mode when the memory module is inserted onto a first type of memory channel with multi-drop data-links; and

operating the memory module in a second mode when the memory module is inserted onto a second type of memory channel with multi-drop data-links.

22. The method of claim 21, wherein the memory module comprises a data (DQ) buffer component coupled to a plurality of device sites, wherein the method further comprises operating the DQ buffer component as a repeater in the first mode and in the second mode.

23. The method of claim 21, wherein the memory module comprises a data (DQ) buffer component coupled to a plurality of device sites, wherein the method further comprises:

operating the DQ buffer component as a repeater in the first mode; and

operating the DQ buffer component as a multiplexer in the second mode.

24. The method of claim 21, further comprising:

coupling a first bi-directional path between a first primary port and a first secondary port in the first mode;

coupling a second bi-directional path between a second primary port and a second secondary port in the first mode;

coupling a third bi-directional path between the first primary port and the second secondary port in the second mode; and

coupling a fourth bi-directional path between the second primary port and the first secondary port in the second mode.

25. A printed circuit board (PCB) comprising:

a plurality of pins;

a plurality of memory devices;

a command and address (CA) buffer component coupled to the plurality of memory devices; and

a plurality of data (DQ) buffer components coupled to the plurality of memory devices, wherein a first DQ buffer component comprises;

a plurality of primary ports coupled to the plurality of pins;

a plurality of secondary ports coupled to the plurality of memory devices; and

a plurality of bi-directional paths between the plurality of primary ports and the plurality of secondary ports,

wherein the first DQ buffer component is programmed to operate the plurality of bi-directional paths in a first configuration when the PCB is inserted onto a first type of memory channel with multi-drop data-links and in a second configuration when the PCB is inserted onto a second type of memory channel with point-to-point data-links.

26. The PCB of claim 25, wherein the plurality of bi-directional paths comprises:

a first bi-directional path between a first primary port and a first secondary port;

a second bi-directional path between a second primary port and a second secondary port;

a third bi-directional path between the first primary port and the second secondary port; and

a fourth bi-directional path between the second primary port and the first secondary port.

27. The PCB of claim 25, further comprising a register to store information to indicate a first mode or a second mode of operation, wherein the first mode corresponds to the first configuration and the second mode corresponds to the second configuration.

28. The PCB of claim 25, further comprising a private bus coupled between the first DQ buffer component and a second DQ buffer component of the plurality of DQ buffer components, wherein the first DQ buffer component further comprises a first private port coupled to the private bus.